NUC130VE3CN Nuvoton Technology Corporation of America, NUC130VE3CN Datasheet - Page 350

• Manufacturer Part Number: NUC130VE3CN
• Description: IC MCU 32BIT 128KB FLASH 100LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™ NUC100r

Specifications of NUC130VE3CN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, EBI/EMI, I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 80
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 16K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Line Control Register (UA_LCR)
Register
UA_LCR
Bits
[31:7]
[6]
[5]
[4]
[3]
[2]
Reserved
31
23
15
7
NuMicro™ NUC130/NUC140 Technical Reference Manual
Descriptions
Reserved
BCB
SPE
EPE
PBE
NSB
Offset
UART0_BA+0x0C R/W
UART1_BA+0x0C R/W
UART2_BA+0x0C R/W
BCB
30
22
14
6
Reserved
Break Control Bit
When this bit is set to logic 1, the serial data output (TX) is forced to the Spacing State
(logic 0). This bit acts only on TX and has no effect on the transmitter logic.
Stick Parity Enable
1 = If bit 3 and 4 are logic 1, the parity bit is transmitted and cheched as logic 0. If bit 3
0 = Stick parity disabled
Even Parity Enable
1 = Even number of logic 1’s is transmitted and checked in each word
0 = Odd number of logic 1’s is transmitted and checked in each word
This bit has effect only when bit 3 (parity bit enable) is set.
Parity Bit Enable
1 = Parity bit is generated on each outgoing character and is checked on each
0 = No parity bit.
Number of “STOP bit”
1= One and a half “ STOP bit” is generated in the transmitted data when 5-bit word
0= One “ STOP bit” is generated in the transmitted data
Two “STOP bit” is generated when 6-, 7- and 8-bit word length is selected.
SPE
29
21
13
R/W
5
si 1 and bit 4 is 0 then the parity bit is transmitted and checked as 1
incoming data.
length is selected;
UART0 Line Control Register
UART1 Line Control Register
UART2 Line Control Register
Description
EPE
28
20
12
4
- 350 -
Reserved
Reserved
Reserved
PBE
27
19
11
3
Publication Release Date: June 14, 2011
NSB
26
18
10
2
25
17
9
1
Revision V2.01
WLS
Reset Value
0x0000_0000
0x0000_0000
0x0000_0000
24
16
8
0