NUC140LD2CN Nuvoton Technology Corporation of America, NUC140LD2CN Datasheet - Page 314

• Manufacturer Part Number: NUC140LD2CN
• Description: IC MCU 32BIT 64KB FLASH 48LQFP
• Manufacturer: Nuvoton Technology Corporation of America
• Series: NuMicro™ NUC100r

Specifications of NUC140LD2CN

• Core Processor: ARM Cortex-M0
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: CAN, I²C, IrDA, LIN, SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 31
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

5.10.6 Register Description
Timer Control Register (TCSR)
Register
TCSR0
TCSR1
TCSR2
TCSR3
DBGACK_TM
Bits
[31]
[30]
[29]
31
23
15
R
7
NuMicro™ NUC130/NUC140 Technical Reference Manual
Offset
TMR_BA01+0x00 R/W
TMR_BA01+0x20 R/W
TMR_BA23+0x00 R/W
TMR_BA23+0x20 R/W
Descriptions
CEN
IE
DBGACK_TMR
CEN
30
22
14
6
R/W
Timer Enable Bit
1 = Starts counting
0 = Stops/Suspends counting
Note1: In stop status, and then set CEN to 1 will enables the 24-bit up-timer keeps up
counting from the last stop counting value.
Note2: This bit is auto-cleared by hardware in one-shot mode (MODE [28:27] =00)
when the associated timer interrupt is generated (IE [29] =1).
Interrupt Enable Bit
1 = Enable timer Interrupt
0 = Disable timer Interrupt
If timer interrupt is enabled, the timer asserts its interrupt signal when the associated
ICE debug mode acknowledge Disable (write-protection bit)
0 = ICE debug mode acknowledgement effects TIMER counting.
TIMER counter will be held while ICE debug mode acknowledged.
1 = ICE debug mode acknowledgement disabled.
TIMER counter will keep going no matter ICE debug mode acknowledged or not.
29
21
13
IE
5
Description
Timer0 Control and Status Register
Timer1 Control and Status Register
Timer2 Control and Status Register
Timer3 Control and Status Register
Reserved
28
20
12
PRESCALE[7:0]
4
- 314 -
MODE[1:0]
Reserved
27
19
11
3
Publication Release Date: June 14, 2011
CRST
26
18
10
2
CACT
25
17
9
1
Revision V2.01
Reset Value
0x0000_0005
0x0000_0005
0x0000_0005
0x0000_0005
TDR_EN
CTB
24
16
8
0