PIC18F4680-H/P Microchip Technology, PIC18F4680-H/P Datasheet - Page 362
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC18F4680-H/P
Manufacturer Part Number
PIC18F4680-H/P
Description
IC MCU 8BIT 64KB FLASH 44PDIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheet
1.PIC18F4585-IPT.pdf
(482 pages)
Specifications of PIC18F4680-H/P
Core Processor
PIC
Core Size
8-Bit
Speed
25MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
36
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.25K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 150°C
Package / Case
40-DIP (0.600", 15.24mm)
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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PIC18F2585/2680/4585/4680
24.5.2
The entire data EEPROM is protected from external
reads and writes by two bits: CPD and WRTD. CPD
inhibits external reads and writes of data EEPROM.
WRTD inhibits internal and external writes to data
EEPROM. The CPU can continue to read and write
data EEPROM regardless of the protection bit settings.
24.5.3
The Configuration registers can be write-protected.
The WRTC bit controls protection of the Configuration
registers. In normal execution mode, the WRTC bit is
readable only. WRTC can only be written via ICSP or
an external programmer.
24.6
Eight memory locations (200000h-200007h) are
designated as ID locations, where the user can store
checksum or other code identification numbers. These
locations are both readable and writable during normal
execution through the TBLRD and TBLWT instructions
or during program/verify. The ID locations can be read
when the device is code-protected.
24.7
PIC18F2585/2680/4585/4680 microcontrollers can be
serially programmed while in the end application circuit.
This is simply done with two lines for clock and data
and three other lines for power, ground and the
programming voltage. This allows customers to
manufacture boards with unprogrammed devices and
then program the microcontroller just before shipping
the product. This also allows the most recent firmware
or a custom firmware to be programmed.
24.8
When the DEBUG Configuration bit is programmed to
a ‘0’, the In-Circuit Debugger functionality is enabled.
This function allows simple debugging functions when
used with MPLAB
this feature enabled, some resources are not available
for general use. Table 24-4 shows which resources are
required by the background debugger.
TABLE 24-4:
DS39625C-page 360
I/O pins:
Stack:
Note:
ID Locations
In-Circuit Debugger
In-Circuit Serial Programming
DATA EEPROM
CODE PROTECTION
CONFIGURATION REGISTER
PROTECTION
Memory resources listed in MPLAB
®
DEBUGGER RESOURCES
IDE. When the microcontroller has
RB6, RB7
2 levels
®
IDE.
Preliminary
To use the In-Circuit Debugger function of the micro-
controller, the design must implement In-Circuit Serial
Programming connections to MCLR/V
V
debugger module available from Microchip or one of
the third party development tool companies.
24.9
The LVP Configuration bit enables Single-Supply ICSP
programming (formerly known as Low-Voltage ICSP
Programming or LVP ). When Single-Supply Program-
ming is enabled, the microcontroller can be programmed
without requiring high voltage being applied to the
MCLR/V
dedicated to controlling Program mode entry and is not
available as a general purpose I/O pin.
While programming using Single-Supply Programming,
V
execution mode. To enter Programming mode, V
applied to the PGM pin.
If Single-Supply ICSP Programming mode will not be
used, the LVP bit can be cleared. RB5/KBI1/PGM then
becomes available as the digital I/O pin, RB5. The LVP
bit may be set or cleared only when using standard
high-voltage programming (V
V
standard high-voltage programming is available and
must be used to program the device.
Memory that is not code-protected can be erased using
either a block erase, or erased row by row, then written
at any specified V
erased, a block erase is required. If a block erase is to
be performed when using Low-Voltage Programming,
the device must be supplied with V
SS
DD
PP
Note 1: High-voltage programming is always avail-
, RB7 and RB6. This will interface to the In-Circuit
/RE3 pin). Once LVP has been disabled, only the
is applied to the MCLR/V
PP
2: While in Low-Voltage ICSP Programming
3: When using Low-Voltage ICSP Program-
4: If the device Master Clear is disabled,
Single-Supply ICSP Programming
/RE3 pin, but the RB5/KBI1/PGM pin is then
able, regardless of the state of the LVP bit,
by applying V
mode, the RB5 pin can no longer be used
as a general purpose I/O pin and should
be held low during normal operation.
ming (LVP) and the pull-ups on PORTB
are enabled, bit 5 in the TRISB register
must be cleared to disable the pull-up on
RB5 and ensure the proper operation of
the device.
verify that either of the following is done to
ensure proper entry into ICSP mode:
a) disable Low-Voltage Programming
b) make certain that RB5/PGM is held
(CONFIG4l<2> = 0); or
low during entry into ICSP.
DD
. If code-protected memory is to be
© 2007 Microchip Technology Inc.
IHH
IHH
to the MCLR pin.
PP
/RE3 pin as in normal
applied to the MCLR/
DD
of 4.5V to 5.5V.
PP
/RE3, V
DD
DD
is
,
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