PIC18F4585-H/P Microchip Technology, PIC18F4585-H/P Datasheet - Page 154
PIC18F4585-H/P
Manufacturer Part Number
PIC18F4585-H/P
Description
IC MCU 8BIT 48KB FLASH 40PDIP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheet
1.PIC18F4585-IPT.pdf
(482 pages)
Specifications of PIC18F4585-H/P
Core Processor
PIC
Core Size
8-Bit
Speed
25MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
36
Program Memory Size
48KB (24K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
3.25K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 150°C
Package / Case
40-DIP (0.600", 15.24mm)
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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PIC18F2585/2680/4585/4680
12.1
Timer1 can operate in one of these modes:
• Timer
• Synchronous Counter
• Asynchronous Counter
The operating mode is determined by the clock select
bit, TMR3CS (T3CON<1>). When TMR3CS is cleared
(= 0), Timer3 increments on every internal instruction
FIGURE 12-1:
FIGURE 12-2:
DS39625C-page 152
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
T1OSO/T13CKI
T1OSO/T13CKI
Note 1: When enable bit T1OSCEN is cleared, the inverter and feedback resistor are turned off to eliminate power drain.
Timer1 Operation
T1OSI
T1OSI
Timer1 Oscillator
Timer1 Oscillator
TIMER1 BLOCK DIAGRAM
TIMER1 BLOCK DIAGRAM (16-BIT READ/WRITE MODE)
T1OSCEN
T1CKPS1:T1CKPS0
T1SYNC
TMR1ON
T1OSCEN
T1CKPS1:T1CKPS0
T1SYNC
TMR1ON
(1)
(1)
TMR1CS
TMR1CS
(CCP1 Special Event Trigger)
(CCP1 Special Event Trigger)
Clear TMR1
Clear TMR1
Clock
Internal
F
Internal
Clock
F
OSC
OSC
/4
/4
Preliminary
On/Off
1
0
1
0
Prescaler
Prescaler
1, 2, 4, 8
1, 2, 4, 8
cycle (Fosc/4). When the bit is set, Timer3 increments
on every rising edge of the Timer1 external clock input
or the Timer1 oscillator, if enabled.
When Timer1 is enabled, the RC1/T1OSI and RC0/
T1OSO/T13CKI pins become inputs. This means the
values of TRISC<1:0> are ignored and the pins are
read as ‘0’.
2
2
TMR1L
TMR1L
8
Synchronize
8
Synchronize
Sleep Input
Sleep Input
Detect
Detect
High Byte
High Byte
TMR1H
TMR1
TMR1
8
© 2007 Microchip Technology Inc.
8
8
Internal Data Bus
1
0
1
0
Read TMR1L
Write TMR1L
on Overflow
on Overflow
TMR1IF
TMR1IF
Set
Set
Timer1
On/Off
Timer1
On/Off
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