LFE2M100SE-7FN1152C Lattice, LFE2M100SE-7FN1152C Datasheet - Page 90
LFE2M100SE-7FN1152C
Manufacturer Part Number
LFE2M100SE-7FN1152C
Description
IC FPGA 95KLUTS 1152FPBGA
Manufacturer
Lattice
Datasheet
1.LFE2M100SE-5FN900C.pdf
(386 pages)
Specifications of LFE2M100SE-7FN1152C
Number Of Logic Elements/cells
*
Number Of Labs/clbs
*
Total Ram Bits
*
Number Of I /o
*
Number Of Gates
*
Voltage - Supply
*
Mounting Type
*
Operating Temperature
*
Package / Case
*
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFE2M100SE-7FN1152C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
SERDES High Speed Data Transmitter (LatticeECP2M Family Only)
Table 3-7. Serial Output Timing and Levels
Table 3-8. Channel Output Jitter - x10 Mode
Table 3-9. Channel Output Jitter - x20 Mode
Deterministic
Random
Total
Deterministic
Random
Total
Deterministic
Random
Total
Deterministic
Random
Total
Note: Values are measured with PRBS 2
x10 mode.
Deterministic
Random
Total
Deterministic
Random
Total
Deterministic
Random
Total
Note: Values are measured with PRBS 2
x20 mode.
V
V
V
V
V
T
T
Z
R
1. All measurements are with 50 ohm impedance.
2. See TN1124,
TX-R
TX-F
TX-OI-SE
TX-DIFF-P-P-1.25
TX-DIFF-P-P-1.4
TX-DIFF-P-P-1.0
TX-DIFF-P-P-1.2
OCM
LTX-RL
Description
Description
Symbol
LatticeECP2M SERDES/PCS Usage Guide
Differential swing (1.25V setting)
Differential swing (1.4V setting)
Differential swing (1.0V setting)
Differential swing (1.2V setting)
Output common mode voltage
Rise time (20% to 80%)
Fall time (80% to 20%)
Output Impedance 50/75/HiZ K Ohms
(single ended)
Return loss (with package)
3.125 Gbps
3.125 Gbps
3.125 Gbps
2.5 Gbps
2.5 Gbps
2.5 Gbps
1.25 Gbps
1.25 Gbps
1.25 Gbps
250 Mbps
250 Mbps
250 Mbps
3.125 Gbps
3.125 Gbps
3.125 Gbps
Frequency
Frequency
1.25 Gbps
1.25 Gbps
1.25 Gbps
2.5 Gbps
2.5 Gbps
2.5 Gbps
Description
7
7
-1, all channels operating, FPGA Logic active, I/Os around SERDES pins quiet, reference clock at
-1, all channels operating, FPGA Logic active, I/Os around SERDES pins quiet, reference clock at
1, 2
1, 2
1, 2
Min.
Min.
1, 2
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
for actual binary settings and the min-max range.
3-38
0.25 to 3.125 Gbps
0.25 to 3.125 Gbps
0.25 to 3.125 Gbps
0.25 to 3.125 Gbps
Frequency
—
—
—
—
—
Typ.
Typ.
0.08
0.22
0.33
0.08
0.20
0.25
0.03
0.14
0.17
0.04
0.12
0.15
0.08
0.27
0.35
0.09
0.23
0.29
0.05
0.16
0.20
DC and Switching Characteristics
LatticeECP2/M Family Data Sheet
Min.
—
—
—
—
—
—
—
—
—
Max.
Max.
0.12
0.38
0.43
0.17
0.25
0.35
0.10
0.19
0.24
0.17
0.13
0.29
0.12
0.51
0.59
0.19
0.34
0.45
0.11
0.22
0.28
50/75
Typ.
1.25
HiZ
1.4
1.0
1.2
0.8
70
70
9
Max.
—
—
—
—
—
—
—
—
—
1, 2
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
UI, p-p
Units
Units
Ohms
V, p-p
V, p-p
V, p-p
V, p-p
Units
dB
ps
ps
V
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