LFXP15C-3FN388I Lattice, LFXP15C-3FN388I Datasheet - Page 20
LFXP15C-3FN388I
Manufacturer Part Number
LFXP15C-3FN388I
Description
IC FPGA 15.4KLUTS 388FPBGA
Manufacturer
Lattice
Datasheet
1.LFXP6C-3TN144C.pdf
(130 pages)
Specifications of LFXP15C-3FN388I
Number Of Logic Elements/cells
*
Number Of Labs/clbs
*
Total Ram Bits
*
Number Of I /o
*
Number Of Gates
*
Voltage - Supply
*
Mounting Type
*
Operating Temperature
*
Package / Case
*
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP15C-3FN388I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
- Current page: 20 of 130
- Download datasheet (779Kb)
Lattice Semiconductor
in selected blocks the input to the DQS delay block. If one of the bypass options is not chosen, the signal first
passes through an optional delay block. This delay, if selected, ensures no positive input-register hold-time require-
ment when using a global clock.
The input block allows two modes of operation. In the single data rate (SDR) the data is registered, by one of the
registers in the single data rate sync register block, with the system clock. In the DDR Mode two registers are used
to sample the data on the positive and negative edges of the DQS signal creating two data streams, D0 and D2.
These two data streams are synchronized with the system clock before entering the core. Further discussion on
this topic is in the DDR Memory section of this data sheet.
Figure 2-21 shows the input register waveforms for DDR operation and Figure 2-22 shows the design tool primi-
tives. The SDR/SYNC registers have reset and clock enable available.
The signal DDRCLKPOL controls the polarity of the clock used in the synchronization registers. It ensures ade-
quate timing when data is transferred from the DQS to the system clock domain. For further discussion of this topic,
see the DDR memory section of this data sheet.
Figure 2-20. Input Register Diagram
(From DDR Polarity
DDRCLKPOL
Control Bus)
DQS Delayed
(From Routing)
(From sysIO
(From DQS
Buffer)
CLK0
Bus)
DI
Delay Block
Fixed Delay
D
D
D-Type
D-Type
DDR Registers
Q
Q
2-17
D1
D
D-Type
Q
D0
D2
LatticeXP Family Data Sheet
SDR & Sync
D
D
/LATCH
/LATCH
D-Type
Registers
D-Type
Q
Q
INCK
INDD
IPOS0
IPOS1
Architecture
Related parts for LFXP15C-3FN388I
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
FPGA - Field Programmable Gate Array 15.4K LUTs 1.8/2.5/3 .3V -3 Spd I
Manufacturer:
Lattice
Part Number:
Description:
FPGA - Field Programmable Gate Array 15.4K LUTs 1.8/2.5/3 .3V -3 Spd
Manufacturer:
Lattice
Part Number:
Description:
FPGA - Field Programmable Gate Array 15.4K LUTs 1.8/2.5/3 .3V -5 Spd
Manufacturer:
Lattice
Part Number:
Description:
FPGA - Field Programmable Gate Array 15.4K LUTs 1.8/2.5/3 .3V -4 Spd I
Manufacturer:
Lattice
Part Number:
Description:
FPGA - Field Programmable Gate Array 15.4K LUTs 268 IO 1. 8/2.5/3.3V -3 Spd
Manufacturer:
Lattice
Part Number:
Description:
FPGA - Field Programmable Gate Array 15.4K LUTs 268 IO 1. 8/2.5/3.3V -3 Spd I
Manufacturer:
Lattice
Part Number:
Description:
FPGA - Field Programmable Gate Array 15.4K LUTS 188 I/O
Manufacturer:
Lattice
Datasheet:
Part Number:
Description:
FPGA LatticeXP Family 15000 Cells 320MHz 130nm (CMOS) Technology 1.8V/2.5V/3.3V 256-Pin FBGA Tray
Manufacturer:
LATTICE SEMICONDUCTOR
Datasheet:
Part Number:
Description:
FPGA LatticeXP Family 15000 Cells 320MHz 130nm (CMOS) Technology 1.8V/2.5V/3.3V 388-Pin FBGA Tray
Manufacturer:
LATTICE SEMICONDUCTOR
Datasheet:
Part Number:
Description:
FPGA LatticeXP Family 15000 Cells 360MHz 130nm (CMOS) Technology 1.8V/2.5V/3.3V 256-Pin FBGA Tray
Manufacturer:
LATTICE SEMICONDUCTOR
Datasheet:
Part Number:
Description:
IC FPGA 15.5KLUTS 300I/O 484-BGA
Manufacturer:
Lattice
Datasheet:
Part Number:
Description:
IC FPGA 15.5KLUTS 188I/O 256-BGA
Manufacturer:
Lattice
Datasheet:
Part Number:
Description:
IC FPGA 15.5KLUTS 268I/O 388-BGA
Manufacturer:
Lattice
Datasheet: