LFEC15E-3FN484I Lattice, LFEC15E-3FN484I Datasheet - Page 19

• Manufacturer Part Number: LFEC15E-3FN484I
• Description: IC FPGA 15.3KLUTS 484FPBGA
• Manufacturer: Lattice

Specifications of LFEC15E-3FN484I

• Number Of Logic Elements/cells: *
• Number Of Labs/clbs: *
• Total Ram Bits: *
• Number Of I /o: *
• Number Of Gates: *
• Voltage - Supply: *
• Mounting Type: *
• Operating Temperature: *
• Package / Case: *
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
Table 2-7. Maximum Number of Elements in a Block
Some options are available in four elements. The input register in all the elements can be directly loaded or can be
loaded as shift registers from previous operand registers. In addition by selecting “dynamic operation” in the
‘Signed/Unsigned’ options the operands can be switched between signed and unsigned on every cycle. Similarly
by selecting ‘Dynamic operation’ in the ‘Add/Sub’ option the Accumulator can be switched between addition and
subtraction on every cycle.
MULT sysDSP Element
This multiplier element implements a multiply with no addition or accumulator nodes. The two operands, A and B,
are multiplied and the result is available at the output. The user can enable the input/output and pipeline registers.
Figure 2-19 shows the MULT sysDSP element.
Figure 2-19. MULT sysDSP Element
MAC sysDSP Element
In this case the two operands, A and B, are multiplied and the result is added with the previous accumulated value.
This accumulated value is available at the output. The user can enable the input and pipeline registers but the out-
put register is always enabled. The output register is used to store the accumulated value. A registered overflow
signal is also available. The overflow conditions are provided later in this document. Figure 2-20 shows the MAC
sysDSP element.
MULT
MAC
MULTADD
MULTADDSUM
Width of Multiply
Multiplicand
Multiplier
Signed
Shift Register B Out
Shift Register B In
n
Input Data
Register B
n
n
n
Register
Input
m
x9
8
2
4
2
Register A
Input Data
m
m
Shift Register A Out
m
Shift Register A In
2-16
Multiplier
m
n
To
Multiplier
x18
Register
Pipeline
x
4
2
2
1
CLK (CLK0,CLK1,CLK2,CLK3)
CE (CE0,CE1,CE2,CE3)
RST(RST0,RST1,RST2,RST3)
LatticeECP/EC Family Data Sheet
(default)
m+n
m+n
x36
—
—
—
1
Output
Architecture