LFEC15E-3FN256I Lattice, LFEC15E-3FN256I Datasheet - Page 36
LFEC15E-3FN256I
Manufacturer Part Number
LFEC15E-3FN256I
Description
IC FPGA 15.3KLUTS 256FPBGA
Manufacturer
Lattice
Datasheet
1.LFECP15E-5FN256C.pdf
(163 pages)
Specifications of LFEC15E-3FN256I
Number Of Logic Elements/cells
*
Number Of Labs/clbs
*
Total Ram Bits
*
Number Of I /o
*
Number Of Gates
*
Voltage - Supply
*
Mounting Type
*
Operating Temperature
*
Package / Case
*
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFEC15E-3FN256I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
- Current page: 36 of 163
- Download datasheet (2Mb)
Lattice Semiconductor
Oscillator
Every LatticeECP/EC device has an internal CMOS oscillator which is used to derive a master clock for configura-
tion. The oscillator and the master clock run continuously. The default value of the master clock is 2.5MHz. Table 2-
15 lists all the available Master Clock frequencies. When a different Master Clock is selected during the design pro-
cess, the following sequence takes place:
1. User selects a different Master Clock frequency.
2. During configuration the device starts with the default (2.5MHz) Master Clock frequency.
3. The clock configuration settings are contained in the early configuration bit stream.
4. The Master Clock frequency changes to the selected frequency once the clock configuration bits are received.
For further information about the use of this oscillator for configuration, please see the list of technical documenta-
tion at the end of this data sheet.
Table 2-15. Selectable Master Clock (CCLK) Frequencies During Configuration
Density Shifting
The LatticeECP/EC family has been designed to ensure that different density devices in the same package have
the same pin-out. Furthermore, the architecture ensures a high success rate when performing design migration
from lower density parts to higher density parts. In many cases, it is also possible to shift a lower utilization design
targeted for a high-density device to a lower density device. However, the exact details of the final resource utiliza-
tion will impact the likely success in each case.
CCLK (MHz)
10.0
2.5*
4.3
5.4
6.9
8.1
9.2
CCLK (MHz)
2-33
13
15
20
26
30
34
41
CCLK (MHz)
LatticeECP/EC Family Data Sheet
130
45
51
55
60
—
—
Architecture
Related parts for LFEC15E-3FN256I
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
IC FPGA 10.2KLUTS 288I/O 484-BGA
Manufacturer:
Lattice
Datasheet:
Part Number:
Description:
FPGA LatticeEC Family 15400 Cells 420MHz 130nm (CMOS) Technology 1.2V 484-Pin FBGA
Manufacturer:
LATTICE SEMICONDUCTOR
Datasheet:
Part Number:
Description:
FPGA LatticeEC Family 15400 Cells 420MHz 130nm (CMOS) Technology 1.2V 484-Pin FBGA
Manufacturer:
Lattice
Datasheet:
Part Number:
Description:
IC FPGA 10.2KLUTS 288I/O 484-BGA
Manufacturer:
Lattice
Datasheet:
Part Number:
Description:
IC FPGA 10.2KLUTS 288I/O 484-BGA
Manufacturer:
Lattice
Datasheet:
Part Number:
Description:
IC FPGA 10.2KLUTS 288I/O 484-BGA
Manufacturer:
Lattice
Datasheet:
Part Number:
Description:
IC FPGA 10.2KLUTS 195I/O 256-BGA
Manufacturer:
Lattice
Datasheet:
Part Number:
Description:
IC FPGA 15.3KLUTS 256FPBGA
Manufacturer:
Lattice
Datasheet:
Part Number:
Description:
IC FPGA 15.3KLUTS 256FPBGA
Manufacturer:
Lattice
Datasheet:
Part Number:
Description:
IC FPGA 15.3KLUTS 484FPBGA
Manufacturer:
Lattice
Datasheet:
Part Number:
Description:
IC FPGA 15.3KLUTS 256FPBGA
Manufacturer:
Lattice
Datasheet:
Part Number:
Description:
IC FPGA 15.3KLUTS 484FPBGA
Manufacturer:
Lattice
Datasheet:
Part Number:
Description:
FPGA - Field Programmable Gate Array 15.4K LUTs 195 I/O
Manufacturer:
Lattice
Part Number:
Description:
FPGA - Field Programmable Gate Array 15.4K LUTs
Manufacturer:
Lattice
Part Number:
Description:
FPGA - Field Programmable Gate Array 15.4K LUTs 195 I/O
Manufacturer:
Lattice