LFEC10E-3FN256I Lattice, LFEC10E-3FN256I Datasheet - Page 51
![no-image](/images/manufacturer_photos/0/3/380/lattice_sml.jpg)
LFEC10E-3FN256I
Manufacturer Part Number
LFEC10E-3FN256I
Description
IC FPGA 10.2KLUTS 256FPBGA
Manufacturer
Lattice
Datasheet
1.LFECP15E-5FN256C.pdf
(163 pages)
Specifications of LFEC10E-3FN256I
Number Of Logic Elements/cells
*
Number Of Labs/clbs
*
Total Ram Bits
*
Number Of I /o
*
Number Of Gates
*
Voltage - Supply
*
Mounting Type
*
Operating Temperature
*
Package / Case
*
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFEC10E-3FN256I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
LatticeECP/EC External Switching Characteristics (Continued)
Figure 3-5. DDR Timings
t
t
f
Primary and Secondary Clock
f
t
t
1. General timing numbers based on LVCMOS2.5V, 12 mA. Loading of 0 pF.
2. Using LVDS I/O standard.
3. DDR timing numbers based on SSTL I/O.
4. DDR specifications are characterized but not tested.
5. UI is average bit period.
6. Based on a single primary clock.
7. These timing numbers were generated using ispLEVER design tool. Exact performance may vary with design and tool version. The tool
Timing v.G 0.30
DQVBS
DQVAS
MAX_DDR
MAX_PRI
W_PRI
SKEW_PRI
Parameter
uses internal parameters that have been characterized but are not tested on every device.
2
Data Valid Before DQS
Data Valid After DQS
DDR Clock Frequency
Frequency for Primary Clock Tree
Clock Pulse Width for Primary
Clock
Primary Clock Skew within an I/O
Bank
Description
DQ and DQS Read Timings
DQS
DQ
DQ and DQS Write Timings
DQS
DQ
6
Over Recommended Operating Conditions
All
All
All
All
All
All
Device
t
DQVBS
t
DVADQ
3-15
t
DVEDQ
Min.
0.20
0.20
1.19
t
DQVAS
95
—
—
-5
Max.
200
420
250
—
—
—
DC and Switching Characteristics
LatticeECP/EC Family Data Sheet
Min.
0.20
0.20
1.19
95
—
—
-4
Max.
166
378
300
—
—
—
Min.
0.20
0.20
1.19
95
—
—
-3
Max.
133
340
350
—
—
—
Units
MHz
MHz
UI
UI
ns
ps
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