SI2109-D-FMR Silicon Laboratories Inc, SI2109-D-FMR Datasheet - Page 21

• Manufacturer Part Number: SI2109-D-FMR
• Manufacturer: Silicon Laboratories Inc

Specifications of SI2109-D-FMR

• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Supplier Unconfirmed

5.6. On-Chip LNB DC-DC Step-Up
Next to the LNB message signaling controller, the
device also integrates the LNB supply regulator
controller.
architecture consists of a step-up dc-dc (boost)
converter followed by an efficient filter, linefeed, and
DiSEqC transmit/receive circuit, which implements a
very power-efficient LNB supply solution. This facilitates
a complete LNB supply circuit with only a minimal
number of external components.
5.7. Crystal Oscillator
The crystal oscillator requires a crystal with a resonant
fundamental frequency of 20 MHz to generate the
reference frequency for the local oscillator. A single
crystal can be shared between two devices by utilizing
the master-slave configuration shown in Figure 11.
6. Operational Description
The following sections discuss the user-programmable
functionality offered by the corresponding register map
sections. Refer to Table 19, “Register Summary,” on
page 38 and detailed register descriptions starting on
page 42.
6.1. System Configuration
The MPEG Transport Stream (TS) output interface
carries the decoded satellite data to external devices for
further processing. Both DVB-S and DSS receiver
modes and associated output data packet formats are
supported. Mode selection is controlled via the system
mode register, SYSM. QPSK or BPSK demodulation is
set via the modulation type (MOD) register.
The MPEG-TS output interface consists of the following
output pins:
TS_DATA[7:0]
TS_CLK
Controller (Si2108/10 Only)
Figure 11. Master-Slave Crystal Sharing
The
XTAL1
XTAL2
XTOUT
Y1
supported
Data
Clock
C11
C12
LNB
XTAL1
supply
regulator
Rev. 1.0
The start of a TS frame is indicated by the TS_SYNC
signal. The TS_SYNC signal is a pulse that is active
during the sync byte in a DVB-S frame or during the first
byte of a DSS frame and is active only while TS
synchronization exists. In serial mode, the TS_SYNC
pulse can be programmed to be active for the whole
byte, or the first bit only, by setting the TSSL bit. The
polarity of the TS_SYNC pulse can be programmed to
be either active high or active low using the TSSP bit.
The TS_VAL output is used to indicate when valid data
is present. TS_VAL is active during the MPEG-TS frame
packet data and inactive while parity data is being
output or when there is no TS synchronization. The
polarity of the TS_VAL output can be programmed to be
active high or active low using the TSVP bit.
The TS_ERR output indicates that an uncorrectable
error has been detected in the RS decoding stage and
that the current TS data packet contains uncorrectable
errors. The TS_ERR output is active during the entire
erred TS frame. The polarity of TS_ERR can be
programmed to be active high or active low using the
TSEP bit.
All signals on the MPEG-TS output interface can be
individually tri-stated using bits TSE_OE, TSV_OE,
TSS_OE, TSC_OE, and TSD_OE.
Transport stream data can be output in a parallel byte-
wide mode or a serial bit-wide mode for system-level
flexibility. Selection of the interface mode is controlled
via the TSM bit. In serial mode, data is output on
TS_DATA[0] while TS_DATA[7:1] are held low. The
direction of the serial data stream may be programmed
to output in an MSB or LSB first direction using the
TSDF bit. Parity data may be optionally zeroed by
setting the TSPG bit. To support board-level timing
modifications, the data stream may be delayed by
setting TSDD.
The transport stream clock can be programmed such
that data is transitioning on its rising or falling edge
using the TSCE bit. In both serial and parallel mode, the
transport stream clock mode bit, TSCM, can be used to
select either a gapped or continuous clock mode. In the
gapped mode, the clock is active only when data is
being output. For this, parity information is not
considered data when the TSPG is set to output zero
data during parity. In the continuous mode, the clock
runs without regard to data being output, and the user
will use TS_VAL as a data strobe. To support board-
level timing modifications, the clock stream may be
delayed by register bit TSCD.
TS_SYNC
TS_VAL
TS_ERR
Si2107/08/09/10
Valid Data Indicator
Uncorrectable Packet Error
Sync/Frame Start Indicator
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