SI2109-D-FM Silicon Laboratories Inc, SI2109-D-FM Datasheet - Page 37

• Manufacturer Part Number: SI2109-D-FM
• Manufacturer: Silicon Laboratories Inc

Specifications of SI2109-D-FM

• Operating Temperature (min): 0C
• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

7. I
The I
supports the 7-bit addressing procedure and is capable of operating at rates up to 400 kbps. Individual data
transfers to and from the device are 8-bits. The I
data line (SDA). The device always operates as a bus slave. Read and write operations are performed in
accordance with the I
The first byte after the START condition consists of the slave address (SLAVE ADR, 7-bits) of the target device.
The slave address is configured during a hard reset by setting the voltage on the ADDR pin. Possible slave
addresses and their corresponding ADDR voltages are listed in Table 18.
Four addresses are available, allowing up to four devices to share the same I
direction of data transfer. During a read operation, data is sent from the device to the bus master. During a write,
data is sent from the bus master to the device. The field labeled “DATA (ADR)” must contain the 8-bit address of
the target register. The data to be transferred to or from the target register must be placed in the following 8-bit
“DATA” field. When the auto-increment feature is enabled, INC_DS, the target register address, is automatically
incremented for subsequent data transfers until a STOP condition ends the operation.
Some registers in the device are larger than the 8-bit DATA field permitted by I
bit addressable chunks that are uniquely identified by a positional suffix. The suffix L indicates the low-byte; the
suffix M indicates the middle-byte (for 24-bit registers only), and the suffix H indicates the high-byte.
To read a multibyte register as a single unit, the low byte must be read first. This forces the device to sample and
hold the contents of the remaining bytes until the multibyte read is complete. If a STOP condition occurs before the
operation is complete, the buffered data is discarded.
To write a multibyte register as a single unit, the low byte must be written first. All bytes must be transferred to the
device before the multibyte value is recorded. If a STOP condition occurs before the operation is complete, the
buffered data is discarded.
The slave address consists of a fixed part and a programmable part. The voltage of the ADDR pin is used to set the
two least significant bits of the address during device power-up according to Table 18. This enables up to four
devices to share the same I
Read O peration
W rite Operation
S
S
A = Acknow ledge
R = Read (1)
W = W rite (0)
2
2
M aster
C bus interface is provided for configuration and monitoring of all internal registers. The Si2107/08/09/10
C Control Interface
SLAVE ADR
SLAVE ADR
Slave
S = START condition
P = STOP condition
S
r
= Repeated START condition
2
C-bus specification and the following sequences.
W
W
A
A
2
C bus.
Fixed Address
DATA (ADR)
Table 18. I
DATA (ADR)
11010
11010
11010
11010
Figure 22. I
2
C Slave Address Selection
2
C bus consists of two wires: a serial clock line (SCL) and a serial
A
A
2
LSBs
C Interface Protocol
Rev. 1.0
00
01
10
11
S
S
r
r
or P
or P
ADDR Voltage (V)
1/3 x V
2/3 x V
0 (pulldown)
V
SLAVE ADR
SLAVE ADR
3.3
(pullup)
3.3
3.3
±10%
±10%
2
Si2107/08/09/10
2
C bus. The R/W bit determines the
C. These registers are split into 8-
R
W
A
A
n bytes + ack
n bytes + ack
DATA
DATA
A/A
A/A
P
P
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