CS5396-KS Cirrus Logic Inc, CS5396-KS Datasheet - Page 33

• Manufacturer Part Number: CS5396-KS
• Description: ADC Dual Delta-Sigma 96KSPS 24-Bit Serial 28-Pin SOIC
• Manufacturer: Cirrus Logic Inc

Specifications of CS5396-KS

• Package: 28SOIC
• Resolution: 24 Bit
• Sampling Rate: 96 KSPS
• Architecture: Delta-Sigma
• Number Of Analog Inputs: 2
• Digital Interface Type: Serial (SPI)
• Input Type: Voltage
• Sample And Hold: Yes
• Polarity Of Input Voltage: Bipolar

S/M - Slave or Master Mode, Pin 17.
CAL - Calibration, Pin 10.
Digital Pin Definitions for CONTROL-PORT MODE
CDIN - Control Port Data Input, Pin 18.
CS - Chip Select Input, Pin 19.
CCLK - Control Port Clock Input, Pin 17.
CAL - Calibration, Pin 10.
Digital Outputs
DACTL- Digital to Analog Control Output, Pin 9.
SDATA1 - Digital Audio Data Output #1, Pin 16.
DS229PP2
When high, the device is configured for Slave mode where LRCK and SCLK are inputs. The
device is configured for Master mode where LRCK and SCLK are outputs when S/M is low.
Activates the calibration of the tri-level delta-sigma modulator.
Control port data input for SPI mode.
Control port data input and output for I
Control port chip select for SPI mode. The CS5396/97 monitors the state of CS during power-
up and will configure to an SPI interface if this pin is held low. Conversely, if held high, the
port will configure to a I
Control port clock input pin for both I
CAL pin is not functional in Control Port Mode and should be connected to ground.
Must be connected to ADCTL. This signal enables communication from the digital circuits to
the analog circuits.
Stand-Alone Mode
Control Port Mode - The 24 audio data bits are presented MSB first, in 2’s complement format.
The audio data can be followed by 8 Peak Signal Level bits which indicate the peak signal
level. The additional audio data options include; 16, 18, or 20-bit data with or without
psychoacoustically optimized dither; or the output of the Low Group Delay filter. The SDATA1
output is completely independent from SDATA2. The mode selection between Stand-Alone and
Control Port mode is determined by the state of the SDATA1 pin during power-up. A 47 k
pull-up resistor on SDATA1 will select the Control Port mode. However, the control port will
not response to CCLK and CDIN until the pull-up on the SDATA1 pin is released.
- The 24-bit audio data is presented MSB first, in 2’s complement format.
2
C interface.
2
C and SPI modes.
2
C mode.
CS5396 CS5397
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