W155G Cypress Semiconductor Corp, W155G Datasheet
W155G
Manufacturer Part Number
W155G
Description
PLL Frequency Timing Generator Single 14.318MHz 16-Pin SOIC
Manufacturer
Cypress Semiconductor Corp
Type
PLL Frequency Timing Generatorr
Datasheet
1.W155G.pdf
(7 pages)
Specifications of W155G
Package
16SOIC
Number Of Elements Per Chip
1
Output Frequency Range
10 to 133 MHz
Operating Temperature
0 to 70 °C
Operating Supply Voltage
3.3|5 V
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
W155G
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Cypress Semiconductor Corporation
Document #: 38-07147 Rev. *A
Features
Overview
The W155 incorporates the latest advances in PLL-based
spread spectrum frequency synthesizer technology. By fre-
quency modulating the SYSCLK output with a low-frequency
carrier, peak EMI can be greatly reduced in a system. Use of
this technique allows systems to pass increasingly difficult EMI
testing without resorting to costly shielding or redesign.
In a system that uses the W155, not only is EMI reduced in the
various clock lines, but also in all signals which are synchro-
nized to SYSCLK. Therefore, the benefits of using this tech-
nique increase with the number of address and data lines in
the system.
The W155 is specifically targeted toward MIPS microproces-
sor based systems where EMI is of particular concern. Each
device uses a single 14.318-MHz crystal to generate a select-
able spread spectrum output and an unmodulated 48-MHz
USB Output.
The spreading function can be disabled by taking the SSON#
pin high. Spread percentage can be selected with the SS%
input (see Table 2 below).
• Generates a spread spectrum timing signal (SYSCLK)
• Requires a 14.318-MHz crystal for operation
• Supports MIPS microprocessor clock frequencies
• Reduces peak EMI by as much as 12 dB
• Integrated loop filter components
• Cycle-to-cycle jitter = 250 ps (max)
• Operates with a 3.3 or 5.0V power supply
• Spread output is selectable from 10 to 133 MHz
• TEST mode supports modulation off (High-Z) and spe-
• Guaranteed 45/55 duty cycle
• Packaged in a 16-pin, 300-mil-wide SOIC (Small Outline
and a non-spread signal (USBCLK)
cial test input reference frequency
Integrated Circuit)
Spread Spectrum Frequency Timing Generator
•
3901 North First Street
Table 1. Frequency Selection (14.318-MHz Reference)
Table 2. Spread Percentage Selection
Note:
1.
Pin Configuration
FS3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Internal pull-up resistor present on inputs marked with ‘*’ and pull-down
resistor present on input marked with ‘^’.
•
GND
FS3*
FS2*
FS1*
VDD
VDD
X1
X2
SS%
San Jose
0
1
FS2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
2
3
4
5
6
7
8
FS1
•
[1]
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
CA 95134
Revised September 24, 2001
16
15
14
13
12
11
10
Spread Percentage
FS0
9
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
–1.25%
–3.75%
TEST
VDD
USBCLK/SS%*
GND
SYSCLK
GND
FS0*
SSON#^
•
(Output Freq.)
133.3 MHz
74.77 MHz
33.33 MHz
16.67 MHz
66.6 MHz
SYSCLK
120 MHz
100 MHz
408-943-2600
70 MHz
60 MHz
50 MHz
40 MHz
30 MHz
25 MHz
20 MHz
12 MHz
10 MHz
W155
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