IS42S16160A-7TL INTEGRATED SILICON SOLUTION (ISSI), IS42S16160A-7TL Datasheet - Page 19

• Manufacturer Part Number: IS42S16160A-7TL
• Description: DRAM Chip SDRAM 256M-Bit 16Mx16 3.3V 54-Pin TSOP-II
• Manufacturer: INTEGRATED SILICON SOLUTION (ISSI)
• Type: SDRAMr

Specifications of IS42S16160A-7TL

• Package: 54TSOP-II
• Density: 256 Mb
• Address Bus Width: 15 Bit
• Operating Supply Voltage: 3.3 V
• Maximum Clock Rate: 143 MHz
• Maximum Random Access Time: 5.4 ns
• Operating Temperature: 0 to 70 °C

IS42S83200A
IS42S16160A
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. D
11/01/05
[ Read Interrupted by Precharge ]
Burst read operation can be interrupted by precharge
of the same bank . READ to PRE interval is minimum 1
CLK. A PRE command to output disable latency is
C L=2
C L=3
Command
Command
Command
Command
Command
Command
(4-bank x 8,388,608 - word x 8-bit)
(4-bank x 4,194,304 - word x 16-bit)
CLK
DQ
DQ
DQ
DQ
DQ
DQ
READ
READ
READ
READ
READ
READ
Read interrupted by Precharge (BL=4)
PRE
PRE
PRE
PRE
Q0
Q0
Q0
equivalent to the /CAS Latency. As a result, READ to
PRE interval determines valid data length to be output.
The figure below shows examples of BL=4.
PRE
PRE
Q1
Q0
Q0
Q0
Q1
Q1
Q2
Q1
Q2
ISSI
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