XCV600E-6FGG680C Xilinx Inc, XCV600E-6FGG680C Datasheet - Page 145
![no-image](/images/no-image-200.jpg)
XCV600E-6FGG680C
Manufacturer Part Number
XCV600E-6FGG680C
Description
FPGA Virtex-E Family 186.624K Gates 15552 Cells 357MHz 0.18um (CMOS) Technology 1.8V 680-Pin FBGA
Manufacturer
Xilinx Inc
Datasheet
1.XCV200E-6CS144C.pdf
(233 pages)
Specifications of XCV600E-6FGG680C
Package
680FBGA
Family Name
Virtex-E
Device Logic Gates
186624
Device Logic Units
15552
Device System Gates
985882
Maximum Internal Frequency
357 MHz
Typical Operating Supply Voltage
1.8 V
Maximum Number Of User I/os
512
Ram Bits
294912
Re-programmability Support
Yes
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Table 19: FG456 Differential Pin Pair Summary
XCV200E, XCV300E
DS022-4 (v2.5) March 14, 2003
Production Product Specification
Notes:
1.
2.
Pair
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
88
89
90
91
92
93
94
95
96
97
98
99
AO in the XCV200E.
AO in the XCV300E.
Bank
5
6
6
6
6
6
6
6
6
6
6
6
6
6
6
6
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
R
Pin
W1
M4
M6
G3
G5
V7
Y2
V3
U4
U2
V1
U1
P3
R1
N5
N4
N2
K2
K3
K5
H1
H3
H4
E2
D2
C1
T1
L4
L1
F2
J2
P
AB3
Pin
W3
R5
R4
R2
N3
N1
M3
H2
G1
H5
V4
Y1
V2
T3
T5
P5
P2
P1
K4
K1
F1
E1
F3
E3
F5
L3
L5
L6
J3
J5
N
AO
√
√
√
√
√
√
2
1
2
√
√
√
2
1
2
√
√
√
2
2
√
√
√
√
2
2
√
√
√
√
√
Functions
Other
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
www.xilinx.com
1-800-255-7778
FG676 Fine-Pitch Ball Grid Array Package
XCV400E and XCV600E devices in the FG676 fine-pitch
Ball Grid Array package have footprint compatibility. Pins
labeled I0_VREF can be used as either in all parts unless
device-dependent as indicated in the footnotes. If the pin is
not used as V
ately following
information.
Table 20: FG676 — XCV400E, XCV600E
Bank
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Virtex™-E 1.8 V Field Programmable Gate Arrays
REF
Table
, it can be used as general I/O. Immedi-
IO_VREF_L2N_YY
IO_VREF_L5N_YY
IO_VREF_L8N_Y
Pin Description
20, see
IO_L1N_YY
IO_L1P_YY
IO_L2P_YY
IO_L5P_YY
IO_L6N_YY
IO_L6P_YY
IO_L0N_Y
IO_L7N_Y
IO_L0P_Y
IO_L7P_Y
IO_L8P_Y
IO_L3N
IO_L3P
IO_L4N
IO_L4P
GCK3
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
Table 21
for Differential Pair
Module 4 of 4
Pin #
D13
A10
B12
G13
E13
A9
B4
B7
C6
C8
D5
C4
G8
C5
D6
D7
G9
D8
C7
A6
B3
F7
E7
A4
F8
B5
E8
A5
F9
E9
1
1
2
1
1
1
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