MT9044AL Zarlink, MT9044AL Datasheet
MT9044AL
Specifications of MT9044AL
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MT9044AL Summary of contents
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... Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2003 - 2005, Zarlink Semiconductor Inc. All Rights Reserved. T1/E1/OC3 System Synchronizer MT9044AP MT9044AL MT9044APR MT9044APR1 MT9044AP1 MT9044AL1 • Accepts reference inputs from two independent sources • JTAG Boundary Scan Applications • ...
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... The RSP, TSP, C6o and C16o are at logic low during reset. The C19o is free-running during reset." Change Example time increases from to 0.9 to1.45 seconds Changed Minimum Schmitt high level input voltage V from 2.3 volts to 3.4 volts SIH 2 Zarlink Semiconductor Inc. Data Sheet ...
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... IC 39 OSCo 2 RSEL 38 OSCi 3 37 MS1 4 VSS 36 MS2 5 F16o 35 TDO 6 RSP 34 LOS1 7 F0o 33 LOS2 8 TSP 32 GTo 9 F8o 31 VSS 10 C1.5o 30 GTi 11 AVDD HOLDOVER Figure 2 - Pin Connections 3 Zarlink Semiconductor Inc. Data Sheet RSEL 32 MS1 31 MS2 30 TDO 29 MT9044AL LOS1 28 LOS2 27 GTo 26 VSS 25 GTi 24 HOLDOVER ...
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... See Figure 20 C1.5o Clock 1.544 MHz (CMOS Output). This output is used in T1 applications AVDD Analog Vdd. + C3o Clock 3.088 MHz (CMOS Output). This output is used in T1 applications. MT9044 Description . nominal. DC nominal Zarlink Semiconductor Inc. Data Sheet . DD ...
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... Mode/Control Select 2 (TTL Input). This input, in conjunction with MS1, determines the device’s mode (Automatic or Manual) and state (Normal, Holdover or Freerun) of operation. The logic level at this input is gated in by the rising edge of F8o. See Table 3. MT9044 Description 5 Zarlink Semiconductor Inc. Data Sheet ...
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... SEC). Both inputs must have the same frequency applied to them. A reset (RST) must be performed after every frequency select input change. Operation with FS1 and FS2 both at logic low is reserved and must not be used. See Table 1. MT9044 Description The logic level at this input is gated Zarlink Semiconductor Inc. Data Sheet . . DD ...
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... MHz Table 1 - Input Frequency Selection TCLR Resets Delay Control Control Signal Circuit Delay Value TIE Corrector Enable from State Machine Figure 3 - TIE Corrector Circuit 7 Zarlink Semiconductor Inc. Data Sheet Virtual Reference to DPLL Compare Circuit Feedback Signal from Frequency Select MUX ...
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... The synchronization method of the DCO is dependent on the state of the MT9044. MT9044 Digitally Limiter Loop Filter Controlled Oscillator State Select from Control Input Impairment Circuit Monitor State Select from State Machine Figure 4 - DPLL Block Diagram 8 Zarlink Semiconductor Inc. Data Sheet DPLL Reference to Output Interface Circuit ...
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... Delay Line E1 Divider Tapped Delay 16 MHz Line Tapped Delay Line 12 MHz DS2 Divider Tapped 19 MHz Delay Line Analog PLL Figure 5 - Output Interface Circuit Block 9 Zarlink Semiconductor Inc. Data Sheet C1.5o C3o C2o C4o C8o C16o F0o F8o F16o C6o C19o ACKo ...
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... Operation section for full details on Automatic Control and Manual Control. RSEL LOS1 LOS2 Figure 6 - Automatic/Manual Control State Machine Block Diagram MT9044 To To TIE To DPLL Reference Corrector State Select MUX Enable Select To and From Automatic/Manual Control Guard Time State Machine Circuit MS1 MS2 10 Zarlink Semiconductor Inc. Data Sheet ...
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... Control MANUAL AUTO MS2 MT9044 RSEL Input Reference 0 PRI 1 SEC 0 State Machine Control 1 Reserved Table 2 - Input Reference Selection MS1 Control Mode 0 MANUAL NORMAL 1 MANUAL HOLDOVER 0 MANUAL FREERUN 1 AUTO State Machine Control Table 3 - Operating Modes and States 11 Zarlink Semiconductor Inc. Data Sheet ...
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... From a reset condition, the MT9044 will take seconds for the output signal to be phase locked to the selected reference. The selection of input references is control dependent as shown in State Tables 4 and 5. The reference frequencies are selected by the frequency control pins FS2 and FS1 as shown in Table 1. MT9044 12 Zarlink Semiconductor Inc. Data Sheet ...
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... SEC). The accuracy of the output clock is equal to the accuracy of the master clock (OSCi ±32 ppm output clock is required, the master clock must also be ±32 ppm. See Applications - Crystal and Clock Oscillator sections. MT9044 13 Zarlink Semiconductor Inc. Data Sheet ...
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... S1H S2H Holdover Primary Secondary (010) (011) Phase Re-Alignment Phase Continuity Maintained (without TIE Corrector Circuit) Phase Continuity Maintained (with TIE Corrector Circuit) 14 Zarlink Semiconductor Inc. Data Sheet State Holdover Holdover (PRI) (SEC) S2 S1H S2H S1 S1 MTIE S1 MTIE S1 MTIE ...
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... S1H S2H Holdover Holdover Primary Secondary (11X) Phase Re-Alignment Phase Continuity Maintained (without TIE Corrector Circuit) Phase Continuity Maintained (with TIE Corrector Circuit) 15 Zarlink Semiconductor Inc. Data Sheet State Holdover Holdover (PRI) (SEC) S2 S1H S2H MTIE S1 MTIE ...
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... Using the above method, the jitter attenuation can be calculated for all combinations of inputs and outputs based on the three jitter transfer functions provided. MT9044 – A ------ 20 ×10 = InputT1 – 18 -------- - 20 × 2.5UI 1UIT1 × --------------------- - = OutputT1 ( ) 1UIE1 ( ) 644ns × ------------------- = OutputT1 = 3.3UI 488ns 16 Zarlink Semiconductor Inc. Data Sheet ...
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... TIE is the time delay between a given timing signal and an ideal timing signal. Maximum Time Interval Error (MTIE) MTIE is the maximum peak to peak delay between a given timing signal and an ideal timing signal within a particular observation period. MTIE MT9044 TIEmax TIEmin – 17 Zarlink Semiconductor Inc. Data Sheet ...
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... TBR 12 December 1993 7. TBR 13 January 1996 8. ITU-T I.431 March 1993 9. ITU-T G.813 August 1996 for Option1 clocks for 2048 kbit/s interfaces 10. ITU-T G.812 June 1998 for type IV clocks for 1,544 kbit/s interfaces and 2,048 kbit/s interfaces MT9044 18 Zarlink Semiconductor Inc. Data Sheet ...
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... Figure 9. Crystal Oscillator - Alternatively, a Crystal Oscillator may be used. A complete oscillator circuit made crystal, resistor and capacitors is shown in Figure 10. MT9044 MT9044 +5 V OSCi + MHz OUT GND 0.1 uF OSCo No Connection Figure 9 - Clock Oscillator Circuit 19 Zarlink Semiconductor Inc. Data Sheet ...
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... MT9044 is returned to its Normal Mode (with no reference switch taking place). Otherwise, the reference input may be changed from Primary to Secondary. MT9044 MT9044 OSCi 20 MHz 1 MΩ OSCo 100 Ω Figure 10 - Crystal Oscillator Circuit Ω Zarlink Semiconductor Inc. Data Sheet 3-50 pF ...
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... V DD × -------------------------------- guard time = RC ln SIH – ≈ × guard time RC 0.6 example ≈ × × guard time 150k 10u 0.6 = 1.45 MT9044 GTo R C 150 kΩ kΩ GTi kΩ 21 Zarlink Semiconductor Inc. Data Sheet ...
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... Holdover to Normal state change. The overall MTIE would only be 350 ns. MT9044 GOOD BAD GOOD PRI PRI PRI NORMAL HOLDOVER × Phase hold = 0.05ppm 2s = 100ns Phase state = 50ns + 200ns = 250ns × Phase 250ns + 100ns = 22 Zarlink Semiconductor Inc. Data Sheet GOOD BAD SEC PRI NORMAL NORMAL 3.5us ...
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... After receiving a good primary signal (LOS1=0), the MT9044 will switch back to Primary Normal Mode For complete Automatic Control state machine details, refer to Table 5 for the State Table, and Figure 8 for the State Diagram. MT9044 MT9044 + kΩ RST kΩ Figure 14 - Power-Up Reset Circuit 23 Zarlink Semiconductor Inc. Data Sheet is for protection P ...
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... Figure 15 - Dual T1 Reference Sources with MT9044 in 1.544 MHz Automatic Control MT9044 MT9044 F0o PRI C4o SEC LOS1 LOS2 + 5 V FS1 MS1 FS2 MS2 GTo RSEL GTi TRST 1 kΩ OSCi RST + kΩ Zarlink Semiconductor Inc. Data Sheet + 5 V 150 kΩ 1 kΩ 1 kΩ CLOCK Out ± 20 MHz 32 ppm ...
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... The external input may come from a device that monitors the status registers of the E1 interfaces, and outputs a logic one in the event of an unacceptable status condition. MT9044 MT9044 PRI SEC LOS1 LOS2 MS1 MS2 RSEL TRST RST CONTROLLER 25 Zarlink Semiconductor Inc. Data Sheet F0o C4o C1. FS1 FS2 GTi CLOCK OSCi Out ± 20 MHz 32 ppm ...
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... C4i Figure 17 - Single Source - E1 to STS-3 with 8 kHz Reference MT9044 MT9044 PRI LOS1 LOS2 MS1 MS2 RSEL TCLR RST 1 kΩ kΩ Zarlink Semiconductor Inc. Data Sheet F0o C4o C1. FS1 FS2 CLOCK Out ± 20 MHz 32 ppm OSCi C19o ACKi ACKo GTi ...
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... 0.7V DD CIH V 0.3V CIL DD V 3.4 SIH V 0.8 SIL V 0.4 HYS I - Zarlink Semiconductor Inc. Data Sheet Min. Max. Units -0.3 7.0 V -0 °C -55 125 900 mW 900 mW ) unless otherwise stated Max. Units 5 °C Conditions/Notes mA Outputs unloaded mA Outputs unloaded ...
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... MHz -36 k +36 k 2.048 MHz -36 k +36 k Sym. Schmitt Zarlink Semiconductor Inc. Data Sheet Units Conditions/Notes† +0 ppm 5-8 +32 ppm 5-8 ppm 5-8 ppm 1,2,4,6-8,40 ppm 1,2,4,6-8,40 ppm 1,2,4,6-8,40 ppm 1-3,6-8 ppm 1-3,6-8 ppm ...
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... R15D t R2D t F0D t F16S t F16H t C15D t C6D t C3D t C2D t C4D t C8D t C16D t TSPD t RSPD t C19D t C15W t C3W t C6W t C2W t C4W t C8W t C16WL t TSPW 29 Zarlink Semiconductor Inc. Data Sheet ORF Min. Max. Units 100 - 337 363 ns 222 238 ns 110 134 -51 - -51 -37 ns -13 2 ...
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... TRST or RST with no further state changes Figure 19 - Input to Output Timing (Normal Mode) MT9044 Sym. t RSPW t C19W t F0WL t F8WH t F16WL t ORF R15D R2D Zarlink Semiconductor Inc. Data Sheet Min. Max. Units 474 491 230 258 ns 111 133 100 ns 100 ns t R8D ...
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... C8W C8W C8o t C4W C4o C2o t C6W C6o t C3W C3o C1.5o t C19W C19o Figure 20 - Output Timing 1 F8o C2o RSP t TSPW TSP Figure 21 - Output Timing 2 Zarlink Semiconductor Inc. MT9044 t F0WL t F16WL t F16S t C16D t C8D t C4W t C4D t t C2D C2W t C6W C3W C3D ...
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... Sym. Min. Max. 0.015 0.010 0.010 0.005 32 Zarlink Semiconductor Inc. Data Sheet Units Conditions/Notes† UIpp 1-14,21-24,28 UIpp 1-14,21-24,28 UIpp 1-14,21-24,28 UIpp 1-14,21-24,29 UIpp 1-14,21-24,30 UIpp 1-14,21-24,31 UIpp ...
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... UIpp 0.010 UIpp 0.005 UIpp Sym. Min. Max. Units Sym. Min. Max. Units Zarlink Semiconductor Inc. Data Sheet Conditions/Notes† 1-14,21-24,30 1-14,21-24,30 1-14,21-24,30 1-14,21-24,30 Conditions/Notes† 1-3,6,9-14,21-22,24,28,35 1-3,6,9-14,21-22,24,28,35 1-3,6,9-14,21-22,24,28,35 1-3,6,9-14,21-22,24,28,35 1-3,6,9-14,21-22,24,28,35 1-3,6,9-14,21-22,24,28,35 Conditions/Notes† 1-3,7,9-14,21-22,24,29,35 1-3,7,9-14,21-22,24,29,35 1-3,7,9-14,21-22,24,29,35 1-3,7,9-14,21-22,24,29,35 1-3,7,9-14,21-22,24,29,35 1-3,7,9-14,21-22,24,29,35 1-3,7,9-14,21-22,24,29,35 ...
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... Units 0.80 UIpp 0.70 UIpp 0.60 UIpp 0.20 UIpp 0.15 UIpp 0.08 UIpp 0.02 UIpp 0.01 UIpp 34 Zarlink Semiconductor Inc. Data Sheet Conditions/Notes† 1-3,8,9-14,21-22,24,30,35 1-3,8,9-14,21-22,24,30,36 1-3,8,9-14,21-22,24,30,35 1-3,8,9-14,21-22,24,30,36 1-3,8,9-14,21-22,24,30,35 1-3,8,9-14,21-22,24,30,36 1-3,8,9-14,21-22,24,30,35 1-3,8,9-14,21-22,24,30,36 1-3,8,9-14,21-22,24,30,35 1-3,8,9-14,21-22,24,30,36 1-3,8,9-14,21-22,24,30,35 1-3,8,9-14,21-22,24,30,36 1-3,8,9-14,21-22,24,30,35 1-3,8,9-14,21-22,24,30,36 Conditions/Notes† 1-3,6,9-14,21-22,24-26,28 ...
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... Max. Units 150 UIpp 140 UIpp 130 UIpp 50 UIpp 40 UIpp 20 UIpp 5 UIpp 1 UIpp 1 UIpp 35 Zarlink Semiconductor Inc. Data Sheet Conditions/Notes† 1-3,7,9-14,21-22,24-26,29 1-3,7,9-14,21-22,24-26,29 1-3,7,9-14,21-22,24-26,29 1-3,7,9-14,21-22,24-26,29 1-3,7,9-14,21-22,24-26,29 1-3,7,9-14,21-22,24-26,29 1-3,7,9-14,21-22,24-26,29 1-3,7,9-14,21-22,24-26,29 1-3,7,9-14,21-22,24-26,29 Conditions/Notes† 1-3,8,9-14,21-22,24-26,30 1-3,8,9-14,21-22,24-26,30 1-3,8,9-14,21-22,24-26,30 1-3,8,9-14,21-22,24-26,30 1-3,8,9-14,21-22,24-26,30 1-3,8,9-14,21-22,24-26,30 1-3,8,9-14,21-22,24-26,30 1-3,8,9-14,21-22,24-26,30 1-3,8,9-14,21-22,24-26,30 ...
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... Master clock duty cycle 40% to 60%. 40. Prior to Holdover Mode, device was in Normal Mode and phase locked. 41. 1 Ulpp = 51 ns for 19.44 MHz signals. MT9044 Sym. Min. Max. Units -0 +0 -32 +32 -100 +100 Zarlink Semiconductor Inc. Data Sheet Conditions/Notes† ppm 15,18 ppm 16,19 ppm 17, ...
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