WJCE6355 Intel, WJCE6355 Datasheet - Page 12

• Manufacturer Part Number: WJCE6355
• Description: Demodulator 64-Pin LQFP
• Manufacturer: Intel

Specifications of WJCE6355

• Package: 64LQFP
• Operating Temperature: -40 to 85 °C

Data Sheet
Figure 5 - FEC Block Diagram
The FSM controller shown in Figure 4 controls both the demodulator and the FEC. It also drives the 2-wire bus to the
tuner. The controller facilitates the automated search of all parameters or any sub-set of parameters of the received
signal. It can also be used to scan any defined frequency range searching for OFDM channels. This mechanism provides
the fast channel scan and acquisition performance, whilst requiring minimal software overhead in the host driver.
The algorithms and architectures used in the CE6355 have been optimized to minimize power consumption.
2.1
The CE6355 has a high performance 10-bit analogue-to-digital converter (ADC) which can sample a 6, 7 or 8 MHz
bandwidth OFDM signal, with its spectrum centred at:
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An on-chip programmable phase locked loop (PLL) is used to generate the ADC sampling clock. The PLL is highly program-
mable allowing a wide choice of sampling frequencies to suit any IF frequency, and all signal bandwidths.
2.2
An AGC module compares the absolute value of the digitized signal with a programmable reference. The error signal is
filtered and is used to control the gain of the amplifier. A sigma-delta modulated output is provided, which has to be RC
low-pass filtered to obtain the voltage to control the amplifier.
The programmable AGC reference has been optimized. A large value for the reference leads to excessive ADC clipping and
a small value results in excessive quantization noise. Hence the optimum value has been determined assuming the input
signal amplitude to be Gaussian distributed. The latter is justified by applying the central limit theorem in statistics to the
OFDM signal, which consists of a large number of randomly modulated carriers. This reference or target value may have to
be lowered slightly for some applications. Slope control bits have been provided for the AGCs and these have to be set
correctly depending on the gain-versus-voltage slope of the gain control amplifiers.
The bandwidth of the AGC is set to a large value for quick acquisition then reduced to a small value for tracking. The AGC
is free running during OFDM channel changes and locks to the new channel while the tuner lock is being established. This
is one of the features of CE6355 used to minimize acquisition time. A robust AGC lock mechanism is provided and the
other parts of the CE6355 begin to acquire only after the AGC has locked.
2.3
Sampling a 36.17 MHz IF signal at 45 MHz results in a spectrally inverted OFDM signal centred at approximately 8.9 MHz.
The first step of the demodulation process is to convert this signal to a complex (in-phase and quadrature) signal in
baseband. A correction for spectral inversion is implemented during this conversion process. Note also that the CE6355
has control mechanisms to search automatically for an unknown spectral inversion status.
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36.17 MHz IF
43.75 MHz IF
5 - 10 MHz near-zero IF
Analogue-to-Digital Converter
Automatic Gain Control
IF to Baseband Conversion
Intel Corporation
CE6355