72821L25TF Integrated Device Technology (Idt), 72821L25TF Datasheet - Page 11

• Manufacturer Part Number: 72821L25TF
• Description: FIFO Mem Sync Quad Depth/Width Bi-Dir 1K x 9 x 2 64-Pin STQFP
• Manufacturer: Integrated Device Technology (Idt)

Specifications of 72821L25TF

• Package: 64STQFP
• Configuration: Quad
• Bus Directional: Bi-Directional
• Density: 18 Kb
• Organization: 1Kx9x2
• Data Bus Width: 9 Bit
• Timing Type: Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 5 V
• Operating Temperature: 0 to 70 °C

NOTE:
1. Only one of the two write enable inputs, WEN1 or WEN2, needs to go inactive to inhibit writes to the FIFO.
NOTE:
1. When t
IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFO
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
(If Applicable)
When
The Latency Timings apply only at the Empty Boundary (EFA, EFB = LOW).
(DB
WENA1, (WENB1)
(QB
WCLKA (WCLKB)
WENA2 (WENB2)
(RENB1, RENB2)
FFA (FFB)
QA
DA
RCLKA (RLCKB)
(WCLKB)
(WENB2)
(WENB1)
RENA1, RENA2
(RCLKB)
(RENB2)
0
WCLKA
WENA2
0
WENA1
RCLKA
RENA1
0
0
- DB
t
(OEB)
- QB
(If Applicable)
SKEW1
SKEW1
- QA
- DA
OEA
OEA (OEB)
(DB
EFA (EFB)
(QB
DA
8
8
QA
8
8
)
)
≥ minimum specification, t
< minimum specification, t
0
LOW
0
0
- DB
0
-QB
- DA
-QA
8
8
8
8
)
)
DATA IN OUTPUT REGISTER
t
t
t
t
ENS
t
ENS
LOW
SKEW1
ENS
DS
NO WRITE
DATA WRITE 1
FRL
FRL
t
ENH
t
DATA IN OUTPUT REGISTER
maximum = 2t
SKEW1
maximum = t
t
t
ENH
ENH
t
A
t
WFF
CLK
CLK
t
FRL
t
t
+ t
ENS
t
REF
+ t
t
ENS
DS
(1)
SKEW1
SKEW1
Figure 9. Empty Flag Timing
Figure 8. Full Flag Timing
or t
CLK
t
+ t
WFF
TM
t
SKEW1
DH
t
t
ENH
11
ENH
t
REF
t
DATA READ
A
t
t
t
ENS
ENS
ENS
NO WRITE
t
DS
DATA WRITE 2
t
ENH
t
A
t
t
SKEW1
SKEW1
t
ENH
t
ENH
t
WFF
DATA READ
COMMERCIAL AND INDUSTRIAL
NEXT DATA READ
t
t
ENS
ENS
t
FRL
(1)
(1)
t
REF
TEMPERATURE RANGES
(1)
JANUARY 13, 2009
NO WRITE
3034 drw 09
3034 drw 10