IS61LPS25632T-166TQ INTEGRATED SILICON SOLUTION (ISSI), IS61LPS25632T-166TQ Datasheet

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IS61LPS25632T-166TQ

Manufacturer Part Number
IS61LPS25632T-166TQ
Description
SRAM Chip Sync Quad 3.3V 8M-Bit 256K x 32 3.5ns 100-Pin TQFP
Manufacturer
INTEGRATED SILICON SOLUTION (ISSI)
Datasheet

Specifications of IS61LPS25632T-166TQ

Package
100TQFP
Timing Type
Synchronous
Density
8 Mb
Data Rate Architecture
SDR
Typical Operating Supply Voltage
3.3 V
Address Bus Width
18 Bit
Number Of I/o Lines
32 Bit
Number Of Ports
4
Number Of Words
256K
I S61LPS25632T/D
IS61LPS25636T/D
IS61LPS51218T/D
FEATURES
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
• Linear burst sequence control using MODE
• Three chip enable option for simple depth
• Common data inputs and data outputs
• JEDEC 100-Pin TQFP package
• Power Supply
• Auto Power-down during deselect
• Single cycle deselect
• Snooze MODE for reduced-power standby
• T Version (three chips selects)
• D Version (two chips selects)
FAST ACCESS TIME
Integrated Silicon Solution, Inc. — www.issi.com —
Rev. B
12/04/03
256K x 32, 256K x 36, 512K x 18
SYNCHRONOUS PIPELINED,
SINGLE-CYCLE DESELECT STATIC RAM
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
control
input
expansion and address pipelining
Symbol
t
t
+3.3V V
+3.3V or 2.5 V
KC
KQ
DD
DDQ
Parameter
Clock Access Time
Cycle Time
Frequency
(I/O)
1-800-379-4774
DESCRIPTION
The
IS61LPS51218T/D are high-speed, low-power synchronous
static RAMs designed to provide burstable, high-performance
memory for communication and networking applications.
The IS61LPS25632T/D is organized as 262,144 words by
32 bits and the IS61LPS25636T/D is organized as 262,144
words by 36 bits. The IS61LPS51218T/D is organized as
524,288 words by 18 bits. Fabricated with
CMOS technology, the device integrates a 2-bit burst
counter, high-speed SRAM core, and high-drive capability
outputs into a single monolithic circuit. All synchronous
inputs pass through registers controlled by a positive-edge-
triggered single clock input.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be one to four
bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
Byte write operation is performed by using byte write enable
(BWE). Input combined with one or more individual byte
write signals (BWx). In addition, Global Write (GW) is
available for writing all bytes at one time, regardless of the
byte write controls.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally and controlled by the ADV (burst address ad-
vance) input pin.
The mode pin is used to select the burst sequence order,
Linear burst is achieved when this pin is tied LOW. Inter-
leave burst is achieved when this pin is tied HIGH or left
floating.
-200
3.1
5
200
ISSI
IS61LPS25632T/D, IS61LPS25636T/D, and
-166
3.5
6
166
Units
ns
ns
MHz
DECEMBER 2003
ISSI
ISSI
's advanced
®
1

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IS61LPS25632T-166TQ Summary of contents

Page 1

... IS61LPS51218T/D are high-speed, low-power synchronous static RAMs designed to provide burstable, high-performance memory for communication and networking applications. The IS61LPS25632T/D is organized as 262,144 words by 32 bits and the IS61LPS25636T/D is organized as 262,144 words by 36 bits. The IS61LPS51218T/D is organized as 524,288 words by 18 bits. Fabricated with ...

Page 2

... IS61LPS25632T/D, IS61LPS25636T/D, IS61LPS51218T/D BLOCK DIAGRAM CLK ADV ADSC ADSP 18/ BWE BWd (x32/x36) BWc (x32/x36) BWb (x32/x36/x18) BWa (x32/x36/x18) CE (T,D) CE2 (T,D) CE2 ( MODE A0 CLK BINARY COUNTER A1 256Kx32; 256Kx36; CLR MEMORY ARRAY 16/17 18/ ADDRESS REGISTER CE CLK 32, 36 DQd BYTE WRITE REGISTERS CLK ...

Page 3

... IS61LPS25632T/D, IS61LPS25636T/D, IS61LPS51218T/D PIN CONFIGURATION 100-Pin TQFP (D Version) 100 DQc 3 DQc 4 V DDQ 5 GND 6 DQc 7 DQc 8 DQc 9 DQc 10 GND 11 V DDQ 12 DQc 13 DQc GND 18 DQd 19 DQd 20 V DDQ 21 GND 22 DQd 23 DQd 24 DQd DQd 25 GND DDQ DQd 28 DQd PIN DESCRIPTIONS A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus ...

Page 4

... IS61LPS25632T/D, IS61LPS25636T/D, IS61LPS51218T/D PIN CONFIGURATION 100-Pin TQFP (D Version) 100 DQPc 1 2 DQc 3 DQc GND 6 DQc 7 DQc 8 DQc 9 DQc 10 GND DQc 13 DQc GND 18 DQd 19 DQd GND DQd 22 DQd 23 DQd 24 DQd 25 GND DQd 28 DQd 29 DQPd PIN DESCRIPTIONS A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus ...

Page 5

... IS61LPS25632T/D, IS61LPS25636T/D, IS61LPS51218T/D PIN CONFIGURATION 100-Pin TQFP (D Version) 100 DDQ 5 GND DQb 8 9 DQb 10 GND V 11 DDQ DQb 12 13 DQb GND 18 DQb DQb DDQ 21 GND 22 DQb DQb 23 24 DQPb GND V 27 DDQ PIN DESCRIPTIONS A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus ...

Page 6

... IS61LPS25632T/D, IS61LPS25636T/D, IS61LPS51218T/D TRUTH TABLE (1-8) ADDRESS CE OPERATION Deselect Cycle, Power-Down None Deselect Cycle, Power-Down None Deselect Cycle, Power-Down None Deselect Cycle, Power-Down None Deselect Cycle, Power-Down None Snooze Mode, Power-Down None Read Cycle, Begin Burst External Read Cycle, Begin Burst ...

Page 7

... IS61LPS25632T/D, IS61LPS25636T/D, IS61LPS51218T/D PARTIAL TRUTH TABLE GW GW BWE BWE BWE BWE BWE Function Read H Read H Write Byte 1 H Write All Bytes H Write All Bytes L OPERATING RANGE Range Ambient Temperature Commercial 0°C to +70°C Industrial -40°C to +85°C LINEAR BURST ADDRESS TABLE (MODE = GND) ...

Page 8

... IS61LPS25632T/D, IS61LPS25636T/D, IS61LPS51218T/D ABSOLUTE MAXIMUM RATINGS Symbol Parameter T Storage Temperature STG P Power Dissipation D I Output Current (per I/O) OUT Voltage Relative to GND for I/O Pins IN OUT V Voltage Relative to GND for IN for Address and Control Inputs V Voltage on V Supply Relative to GND DD DD Notes: 1 ...

Page 9

... IS61LPS25632T/D, IS61LPS25636T/D, IS61LPS51218T/D POWER SUPPLY CHARACTERISTICS Symbol Parameter Test Conditions I AC Operating Device Selected Supply Current IH All Inputs V Cycle Time t I Standby Current Device Deselected, SB TTL Input V = Max., DD All Inputs Standby Current Device Deselected, SBI CMOS Input V = Max GND + 0. Note: 1. MODE pin has an internal pullup and should be tied to V GND + 0 ...

Page 10

... IS61LPS25632T/D, IS61LPS25636T/D, IS61LPS51218T/D (1,2) CAPACITANCE Symbol Parameter C Input Capacitance IN C Input/Output Capacitance OUT Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions 25° MHz 3.3V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times ...

Page 11

... IS61LPS25632T/D, IS61LPS25636T/D, IS61LPS51218T/D 2.5V I/O AC TEST CONDITIONS Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load 2.5V I/O OUTPUT LOAD EQUIVALENT OUTPUT Figure 3 Integrated Silicon Solution, Inc. — www.issi.com — Rev. B 12/04/03 Unit ...

Page 12

... IS61LPS25632T/D, IS61LPS25636T/D, IS61LPS51218T/D Read/WRITE CYCLE SWITCHING CHARACTERISTICS Symbol Parameter f Clock Frequency MAX t Cycle Time KC t Clock High Pulse Width KH t Clock Low Pulse Width KL t Clock Access Time KQ t (1) Clock High to Output Invalid KQX t (1,2) Clock High to Output Low-Z KQLZ t (1,2) ...

Page 13

... IS61LPS25632T/D, IS61LPS25636T/D, IS61LPS51218T/D READ/WRITE CYCLE TIMING CLK ADSP ADSC ADV Address RD1 BWE BWx t t CES CEH CES CEH CE2 t t CES CEH CE2 t OEQ OE t OELZ High-Z DATA OUT t KQLZ High-Z DATA IN Single Read Integrated Silicon Solution, Inc. — www.issi.com — ...

Page 14

... IS61LPS25632T/D, IS61LPS25636T/D, IS61LPS51218T/D WRITE CYCLE SWITCHING CHARACTERISTICS Symbol Parameter t Cycle Time KC t Clock High Pulse Width KH t Clock Low Pulse Width KL t Address Setup Time AS t Address Status Setup Time SS t Write Setup Time WS t Data In Setup Time DS t Chip Enable Setup Time ...

Page 15

... IS61LPS25632T/D, IS61LPS25636T/D, IS61LPS51218T/D WRITE CYCLE TIMING CLK ADSP ADSC ADV must be inactive for ADSP Write ADV Address WR1 BWE t WS BWx WR1 t t CES CEH CES CEH CE2 t t CES CEH CE2 OE High-Z DATA OUT t DS High-Z DATA IN 1a Single Write Integrated Silicon Solution, Inc. — ...

Page 16

... IS61LPS25632T/D, IS61LPS25636T/D, IS61LPS51218T/D SNOOZE MODE ELECTRICAL CHARACTERISTICS Symbol Parameter I Current during SNOOZE MODE inactive to input sampled PUS t ZZ active to SNOOZE current ZZI t ZZ inactive to exit SNOOZE current RZZI SNOOZE MODE TIMING CLK t PDS ZZ setup cycle ZZ t ZZI Isupply I SB2 All Inputs ...

Page 17

... IS61LPS25636D-166TQ Integrated Silicon Solution, Inc. — www.issi.com — Rev. B 12/04/03 (T Version) Industrial Range: -40°C to +85°C Speed Order Part Number Package 166Mhz IS61LPS25632T-166TQI TQFP Package TQFP (T Version) Industrial Range: -40°C to +85°C Package Speed Order Part Number TQFP 166Mhz IS61LPS25636T-166TQI ...

Page 18

... IS61LPS25632T/D, IS61LPS25636T/D, IS61LPS51218T/D ORDERING INFORMATION: IS61LPS51218 (T Version) Commercial Range: 0°C to +70°C Speed Order Part Number 166Mhz IS61LPS51218T-166TQ (D Version) Commercial Range: 0°C to +70°C Speed Order Part Number 166Mhz IS61LPS51218D-166TQ 18 (T Version) Industrial Range: -40°C to +85°C Speed Order Part Number ...

Page 19

PACKAGING INFORMATION TQFP (Thin Quad Flat Pack Package) Package Code Thin Quad Flat Pack (TQ) Millimeters Inches Symbol Min Max Min Ref. Std. No. Leads (N) 100 A — 1.60 — A1 0.05 0.15 ...

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