MT90826AL Zarlink, MT90826AL Datasheet - Page 21

• Manufacturer Part Number: MT90826AL
• Description: Switch Fabric 4K x 4K/2K x 2K/1K x 1K 3.3V 160-Pin MQFP Tray
• Manufacturer: Zarlink

Specifications of MT90826AL

• Package: 160MQFP
• Number Of Ports: 32
• Fabric Size: 4K x 4K|2K x 2K|1K x 1K
• Switch Core: Non-Blocking
• Port Speed: 2.048|4.096|8.192|16.384 Mbps
• Operating Supply Voltage: 3.3 V

15 - 11
10
9
8 - 0
Bit
FE4
15
Read/Write Address:
Reset Value:
CFE
FD9
FD8-0
FE3
FE4-0
14
Name
FE2
13
FE1
12
Table 7 - Frame Alignment (FAR) Register Bits
FE0
11
Frame Evaluation Input Select. The binary value expressed in these bits
refers to the frame evaluation inputs, FEi0 to FEi31.
Complete Frame Evaluation. When CFE = 1, the frame evaluation is
completed and FD9 to FD0 bits contains a valid frame alignment offset.
This bit is reset to zero, when SFE bit in the control register is changed from 1
to 0.
Frame Delay Bit 9. The falling edge of FEi input is sampled during the internal
master clock high phase (FD9 = 1) or during the low phase (FD9 = 0). This bit
allows the measurement resolution to 1/2 internal master clock cycle.
See Figure 5 for clock signal alignment.
Frame Delay Bits. The binary value expressed in these bits refers to the
measured input offset value. These bits are reset to zero when the SFE bit of
the control register changes from 1 to 0. (FD8 = MSB, FD0 = LSB)
0001
0000
Internal Master Clock
CFE
10
H
H
,
.
C8i
C16i
C32i
FD9
Zarlink Semiconductor Inc.
9
MT90826
FD8
8
21
FD7
7
8 Mbps, 16 Mbps, 4&8 Mbps, 16&8 Mbps
FD6
6
Operation Mode
Description
4 Mbps, 2&4 Mbps
2 Mbps
FD5
5
FD4
4
FD3
3
FD2
2
FD1
1
Data Sheet
FD0
0