XC3195A-3PC84C Xilinx Inc, XC3195A-3PC84C Datasheet - Page 66

• Manufacturer Part Number: XC3195A-3PC84C
• Description: FPGA XC3100A Family 7.5K Gates 484 Cells 270MHz CMOS Technology 5V 84-Pin PLCC
• Manufacturer: Xilinx Inc

Specifications of XC3195A-3PC84C

• Package: 84PLCC
• Family Name: XC3100A
• Device Logic Units: 484
• Device System Gates: 7500
• Number Of Registers: 1320
• Maximum Internal Frequency: 270 MHz
• Typical Operating Supply Voltage: 5 V
• Maximum Number Of User I/os: 70
• Ram Bits: 94944
• Re-programmability Support: Yes
• Dc: 0029

XC3000 Series Field Programmable Gate Arrays
XC3064A/XC3090A/XC3195A 84-Pin PLCC Pinouts
XC3000A, XC3000L, XC3100A, and XC3100L families have identical pinouts
Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs.
Programmed outputs are default slew-rate limited.
* In the PC84 package, XC3064A, XC3090A and XC3195A have additional VCC and GND pins and thus a different pin
definition than XC3020A/XC3030A/XC3042A.
7-68
PLCC Pin Number
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
XC3064A, XC3090A, XC3195A
XTL2(IN)-I/O
TCLKIN-I/O
M1-RDATA
M0-RTRIG
HDC-I/O
INIT/I/O*
PWRDN
LDC-I/O
M2-I/O
GND*
VCC*
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PLCC Pin Number
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
10
11
1
2
3
4
5
6
7
8
9
November 9, 1998 (Version 3.1)
XC3064A, XC3090A, XC3195A
XTL1(OUT)-BCLKIN-I/O
RDY/BUSY-RCLK-I/O
A1-CS2-I/O
D0-DIN-I/O
A0-WS-I/O
DONE-PG
DOUT-I/O
CS1-I/O*
A13-I/O*
A12-I/O*
CS0-I/O
A15-I/O
A14-I/O
A11-I/O
A10-I/O
RESET
D3-I/O*
D2-I/O*
A6-I/O*
A7-I/O*
D7-I/O
D6-I/O
D5-I/O
D4-I/O
D1-I/O
A2-I/O
A3-I/O
A4-I/O
A5-I/O
A8-I/O
A9-I/O
CCLK
GND*
VCC*
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
R