HD6412340TE20 Renesas Electronics America, HD6412340TE20 Datasheet
HD6412340TE20
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HD6412340TE20 Summary of contents
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To our customers, Old Company Name in Catalogs and Other Documents st On April 1 , 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the ...
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All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm ...
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H8S/2345 Group, 16 H8S/2345 F-ZTAT Hardware Manual Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2300 Series The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be ...
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Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead ...
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General Precautions on the Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are used as ...
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Rev. 4.00 Feb 15, 2006 page iv of xxiv ...
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The H8S/2345 Group is a series of high-performance microcontrollers with a 32-bit H8S/2000 CPU core, and a set of on-chip supporting functions required for system configuration. The H8S/2000 CPU can execute basic instructions in one state, and is provided with ...
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Rev. 4.00 Feb 15, 2006 page vi of xxiv ...
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Main Revisions in This Edition Item Page All — 9.7 Usage Notes 370 Figure 9.57 Contention between TCNT Write and Overflow 11.2.2 Timer 399 Control/Status Register (TCSR) 14.4.3 Input Sampling 521 and A/D Conversion Time Figure 14.5 A/D Conversion Timing ...
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Item Page 20.1.6 Flash Memory 648 Characteristics Table 20.10 Flash Memory Characteristics 649 Appendix G Package 897 Dimensions Figure G.1 TFP-100B Package Dimensions Figure G.2 TFP-100G 898 Package Dimensions Figure G.3 FP-100A 899 Package Dimensions Figure G.4 FP-100B 900 Package ...
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Section 1 Overview ............................................................................................................. 1.1 Overview........................................................................................................................... 1.2 Block Diagram .................................................................................................................. 1.3 Pin Description.................................................................................................................. 1.3.1 Pin Arrangement .................................................................................................. 1.3.2 Pin Functions in Each Operating Mode ............................................................... 1.3.3 Pin Functions ....................................................................................................... 14 Section 2 CPU ...................................................................................................................... 21 2.1 Overview........................................................................................................................... 21 2.1.1 Features................................................................................................................ ...
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Power-Down State ............................................................................................... 61 2.9 Basic Timing ..................................................................................................................... 62 2.9.1 Overview.............................................................................................................. 62 2.9.2 On-Chip Memory (ROM, RAM) ......................................................................... 62 2.9.3 On-Chip Supporting Module Access Timing ...................................................... 64 2.9.4 External Address Space Access Timing .............................................................. 65 Section 3 MCU Operating ...
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Reset Sequence .................................................................................................... 93 4.2.4 Interrupts after Reset............................................................................................ 94 4.2.5 State of On-Chip Supporting Modules after Reset Release ................................. 94 4.3 Traces................................................................................................................................ 95 4.4 Interrupts ........................................................................................................................... 96 4.5 Trap Instruction................................................................................................................. 97 4.6 Stack Status after Exception Handling.............................................................................. 98 4.7 ...
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Section 6 Bus Controller 6.1 Overview........................................................................................................................... 129 6.1.1 Features................................................................................................................ 129 6.1.2 Block Diagram ..................................................................................................... 130 6.1.3 Pin Configuration................................................................................................. 131 6.1.4 Register Configuration......................................................................................... 131 6.2 Register Descriptions ........................................................................................................ 132 6.2.1 Bus Width Control Register (ABWCR)............................................................... 132 6.2.2 Access State Control Register ...
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Bus Transfer Timing ............................................................................................ 169 6.8.4 External Bus Release Usage Note........................................................................ 169 6.9 Resets and the Bus Controller ........................................................................................... 169 Section 7 Data Transfer Controller 7.1 Overview........................................................................................................................... 171 7.1.1 Features................................................................................................................ 171 7.1.2 Block Diagram ..................................................................................................... 172 7.1.3 Register Configuration......................................................................................... ...
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Port 2................................................................................................................................. 217 8.3.1 Overview.............................................................................................................. 217 8.3.2 Register Configuration......................................................................................... 218 8.3.3 Pin Functions ....................................................................................................... 220 8.4 Port 3................................................................................................................................. 228 8.4.1 Overview.............................................................................................................. 228 8.4.2 Register Configuration......................................................................................... 228 8.4.3 Pin Functions ....................................................................................................... 231 8.5 Port 4................................................................................................................................. 233 8.5.1 Overview.............................................................................................................. 233 8.5.2 ...
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Port G................................................................................................................................ 270 8.12.1 Overview.............................................................................................................. 270 8.12.2 Register Configuration......................................................................................... 271 8.12.3 Pin Functions ....................................................................................................... 274 Section 9 16-Bit Timer Pulse Unit (TPU) 9.1 Overview........................................................................................................................... 277 9.1.1 Features................................................................................................................ 277 9.1.2 Block Diagram ..................................................................................................... 281 9.1.3 Pin Configuration................................................................................................. 282 9.1.4 Register ...
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Section 10 8-Bit Timers 10.1 Overview........................................................................................................................... 371 10.1.1 Features................................................................................................................ 371 10.1.2 Block Diagram ..................................................................................................... 372 10.1.3 Pin Configuration................................................................................................. 373 10.1.4 Register Configuration......................................................................................... 373 10.2 Register Descriptions ........................................................................................................ 374 10.2.1 Timer Counters 0 and 1 (TCNT0, TCNT1) ......................................................... 374 10.2.2 Time ...
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Notes on Register Access..................................................................................... 402 11.3 Operation .......................................................................................................................... 404 11.3.1 Watchdog Timer Operation ................................................................................. 404 11.3.2 Interval Timer Operation ..................................................................................... 405 11.3.3 Timing of Setting Overflow Flag (OVF) ............................................................. 406 11.3.4 Timing of Setting of Watchdog Timer Overflow Flag ...
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Features................................................................................................................ 477 13.1.2 Block Diagram ..................................................................................................... 478 13.1.3 Pin Configuration................................................................................................. 479 13.1.4 Register Configuration......................................................................................... 480 13.2 Register Descriptions ........................................................................................................ 481 13.2.1 Smart Card Mode Register (SCMR) .................................................................... 481 13.2.2 Serial Status Register (SSR) ................................................................................ 482 13.2.3 Serial Mode Register ...
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Features................................................................................................................ 529 15.1.2 Block Diagram ..................................................................................................... 530 15.1.3 Pin Configuration................................................................................................. 531 15.1.4 Register Configuration......................................................................................... 531 15.2 Register Descriptions ........................................................................................................ 532 15.2.1 D/A Data Registers 0 and 1 (DADR0, DADR1) ................................................. 532 15.2.2 D/A Control Register (DACR) ............................................................................ 532 15.2.3 ...
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Register Configuration......................................................................................... 563 17.7 Register Descriptions ........................................................................................................ 564 17.7.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 564 17.7.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 566 17.7.3 Erase Block Registers 1 and 2 (EBR1, EBR2)..................................................... 568 17.7.4 System Control Register 2 ...
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Register Descriptions ........................................................................................................ 616 18.2.1 System Clock Control Register (SCKCR) ........................................................... 616 18.3 Oscillator........................................................................................................................... 617 18.3.1 Connecting a Crystal Resonator........................................................................... 617 18.3.2 External Clock Input ............................................................................................ 619 18.4 Duty Adjustment Circuit................................................................................................... 621 18.5 Medium-Speed Clock Divider .......................................................................................... 621 18.6 ...
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Absolute Maximum Ratings ................................................................................ 650 20.2.2 DC Characteristics ............................................................................................... 651 20.2.3 AC Characteristics ............................................................................................... 656 20.2.4 A/D Conversion Characteristics........................................................................... 663 20.2.5 D/A Conversion Characteristics........................................................................... 664 20.3 Operation Timing.............................................................................................................. 665 20.3.1 Clock Timing ....................................................................................................... 665 20.3.2 Control Signal Timing ......................................................................................... ...
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Appendix E Timing of Transition to and Recovery from Hardware Standby Mode Appendix F Product Code Lineup Appendix G Package Dimensions .............................................................................................. 895 ................................................................................. 896 .................................................................................. 897 Rev. 4.00 Feb 15, 2006 page xxiii of xxiv ...
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Rev. 4.00 Feb 15, 2006 page xxiv of xxiv ...
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Overview The H8S/2345 Group is a series of microcomputers (MCUs: microcomputer units), built around the H8S/2000 CPU, employing Renesas’ proprietary architecture, and equipped with peripheral functions on-chip. The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen ...
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Section 1 Overview Table 1.1 Overview Item Specification CPU General-register machine Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) High-speed operation suitable for realtime control Maximum clock rate: 20 MHz High-speed arithmetic operations 8/16/32-bit ...
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Item Specification 16-bit timer-pulse 6-channel 16-bit timer on-chip unit (TPU) Pulse I/O processing capability for pins' Automatic 2-phase encoder count capability 8-bit timer 8-bit up-counter (external event count capability) 2 channels Two time constant registers Two-channel connection ...
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Section 1 Overview Item Specification Power-down state Medium-speed mode Sleep mode Module stop mode Software standby mode Hardware standby mode Operating modes Eight MCU operating modes (F-ZTAT version) CPU Operating Mode Mode 0 — Advanced 5 ...
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Item Specification Operating modes Seven MCU operating modes (ZTAT, mask ROM, and ROMless versions) CPU Operating Mode Mode 1 Normal Advanced On-chip ROM disabled Note: * Not used on ROMless ...
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Section 1 Overview 1.2 Block Diagram Figure 1.1 shows an internal block diagram of the H8S/2345 Group EXTAL XTAL STBY RES WDTOVF (FWE NMI / /RD ...
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Pin Description 1.3.1 Pin Arrangement Figures 1.2 and 1.3 show the pin arrangement of the H8S/2345 Group. PF /BREQ/IRQ0 ref P4 /AN0 /AN1 /AN2 81 2 ...
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Section 1 Overview P4 /AN0 /AN1 /AN2 /AN3 /AN4 /AN5 /AN6/DA0 /AN7/DA1 ...
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Pin Functions in Each Operating Mode Table 1.2 shows the pin functions of the H8S/2345 Group in each of the operating modes. Table 1.2 Pin Functions in Each Operating Mode Pin No. FP-100B, TFP-100B, Mode Mode ...
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Section 1 Overview Pin No. FP-100B, TFP-100B, Mode Mode TFP-100G FP-100A ...
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Pin No. FP-100B, TFP-100B, Mode Mode TFP-100G FP-100A TIOCA3 TIOCA3 ...
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Section 1 Overview Pin No. FP-100B, TFP-100B, Mode Mode TFP-100G FP-100A BREQ/ BREQ/ IRQ0 IRQ0 ref ref ...
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Pin No. FP-100B, TFP-100B, Mode Mode TFP-100G FP-100A TIOCA0 TIOCA0 100 TIOCB0 TIOCB0 Notes: 1. Modes are not available on the ...
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Section 1 Overview 1.3.3 Pin Functions Table 1.3 outlines the pin functions of the H8S/2345 Group. Table 1.3 Pin Functions Type Symbol Power supply Clock XTAL EXTAL Rev. 4.00 Feb 15, 2006 page 14 of 900 ...
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Type Symbol Operating mode control MD 0 Pin No. FP-100B, TFP-100B, I/O TFP-100G FP-100A 61, 58, 63, 60, Input 57 59 Rev. 4.00 Feb 15, 2006 page 15 of 900 Section 1 Overview Name and Function Mode ...
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Section 1 Overview Type Symbol Operating mode control MD 0 RES System control STBY BREQ BACK FWE * 1 Rev. 4.00 Feb 15, 2006 page 16 of 900 REJ09B0291-0400 Pin No. FP-100B, TFP-100B, I/O TFP-100G FP-100A 61, ...
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Type Symbol Interrupts NMI IRQ7 to IRQ0 Address bus Data bus CS3 to Bus control CS0 AS RD HWR LWR WAIT Pin No. FP-100B, TFP-100B, I/O TFP-100G FP-100A 63 65 ...
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Section 1 Overview Type Symbol 16-bit timer- TCLKD to pulse unit TCLKA (TPU) TIOCA0, TIOCB0, TIOCC0, TIOCD0 TIOCA1, TIOCB1 TIOCA2, TIOCB2 TIOCA3, TIOCB3, TIOCC3, TIOCD3 TIOCA4, TIOCB4 TIOCA5, TIOCB5 8-bit timer TMO0, TMO1 TMCI0, TMCI1 TMRI0, TMRI1 WDTOVF * 2 ...
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Type Symbol Serial TxD1, communication TxD0 interface (SCI) RxD1, Smart Card RxD0 interface SCK1 SCK0 A/D converter AN7 to AN0 ADTRG D/A converter DA1, DA0 A/D converter AV CC and D/A converters ref I/O ports P1 to ...
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Section 1 Overview Type Symbol I/O ports ...
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Overview The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte (architecturally 4-Gbyte) linear ...
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Section 2 CPU High-speed operation All frequently-used instructions execute in one or two states Maximum clock rate 8/16/32-bit register-register add/subtract : 8-bit register-register multiply 16 ÷ 8-bit register-register divide 16 16-bit register-register multiply 32 ÷ 16-bit register-register ...
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Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements. More general registers and control registers Eight 16-bit expanded registers, and one 8-bit control register, have been added. Expanded address space Normal ...
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Section 2 CPU 2.2 CPU Operating Modes The H8S/2000 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address space (architecturally a maximum 16-Mbyte program area ...
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Exception Vector Table and Memory Indirect Branch Addresses: In normal mode the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits. The configuration of the exception vector table in ...
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Section 2 CPU Stack Structure: When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are ...
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Exception Vector Table and Memory Indirect Branch Addresses: In advanced mode the top area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and ...
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Section 2 CPU Stack Structure: In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception ...
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Address Space Figure 2.6 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 64-kbyte address space in normal mode * , and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced ...
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Section 2 CPU 2.4 Register Configuration 2.4.1 Overview The CPU has the internal registers shown in figure 2.7. There are two types of registers: general registers and control registers. General Registers (Rn) and Extended Registers (En) 15 ER0 ER1 ER2 ...
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General Registers The CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can ...
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Section 2 CPU SP (ER7) 2.4.3 Control Registers The control registers are the 24-bit program counter (PC), 8-bit extended control register (EXR), and 8-bit condition-code register (CCR). (1) Program Counter (PC) This 24-bit counter indicates the address of the next ...
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Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Bit 7—Interrupt Mask Bit (I): Masks interrupts other than ...
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Section 2 CPU Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The and C flags are used as branching conditions for conditional branch (Bcc) instructions. 2.4.4 Initial Register ...
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Data Formats The CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit … byte operand data. The ...
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Section 2 CPU Data Type Register Number Word data Rn Word data En 15 MSB Longword data ERn 31 MSB En Legend: ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: General ...
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Memory Data Formats Figure 2.11 shows the data formats in memory. The CPU can access word data and longword data in memory, but word or longword data must begin at an even address attempt is made to ...
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Section 2 CPU 2.6 Instruction Set 2.6.1 Overview The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function in table 2.1. Table 2.1 Instruction Classification Function Instructions Data transfer MOV POP * , PUSH * 1 ...
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Instructions and Addressing Modes Table 2.2 indicates the combinations of instructions and addressing modes that the H8S/2600 CPU can use. Table 2.2 Combinations of Instructions and Addressing Modes Function Instruction Data MOV BWL BWL BWL BWL BWL BWL transfer ...
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Section 2 CPU Function Instruction System TRAPA — control RTE — SLEEP — LDC B STC — ANDC, ORC, B XORC NOP — Block data transfer — Legend: B: Byte W: Word L: Longword Note: * Cannot be used in ...
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Table of Instructions Classified by Function Table 2.3 summarizes the instructions in each functional category. The notation used in table 2.3 is defined below. Operation Notation General register (destination General register (source General register * ...
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Section 2 CPU Table 2.3 Instructions Classified by Function Type Instruction Data transfer MOV MOVFPE MOVTPE POP PUSH LDM STM Arithmetic ADD operations SUB ADDX SUBX INC DEC ADDS SUBS Rev. 4.00 Feb 15, 2006 page 42 of 900 REJ09B0291-0400 ...
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Type Instruction Arithmetic DAA operations DAS MULXU MULXS DIVXU DIVXS CMP NEG EXTU EXTS TAS Size * Function B Rd decimal adjust Decimal-adjusts an addition or subtraction result in a general register by referring to the CCR to produce 4-bit ...
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Section 2 CPU Type Instruction Logic AND operations OR XOR NOT Shift SHAL operations SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR Bit- BSET manipulation instructions BCLR BNOT BTST Rev. 4.00 Feb 15, 2006 page 44 of 900 REJ09B0291-0400 Size * ...
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Type Instruction Bit- BAND manipulation instructions BIAND BOR BIOR BXOR BIXOR BLD BILD BST BIST Size * Function B C (<bit-No.> of <EAd>) ANDs the carry flag with a specified bit in a general register or memory operand and stores ...
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Section 2 CPU Type Instruction Branch Bcc instructions JMP BSR JSR RTS System TRAPA control RTE instructions SLEEP LDC Rev. 4.00 Feb 15, 2006 page 46 of 900 REJ09B0291-0400 Size * Function — Branches to a specified address if a ...
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Type Instruction System STC control instructions ANDC ORC XORC NOP Block data EEPMOV.B transfer instruction EEPMOV.W Note: * Size refers to the operand size. B: Byte W: Word L: Longword Size * Function B/W CCR (EAd), EXR Transfers CCR or ...
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Section 2 CPU 2.6.4 Basic Instruction Formats The CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field (cc). ...
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Addressing Modes and Effective Address Calculation 2.7.1 Addressing Mode The CPU supports the eight addressing modes listed in table 2.4. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and ...
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Section 2 CPU (4) Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn: Register indirect with post-increment—@ERn+ The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. After the operand is ...
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Immediate—#xx:8, #xx:16, or #xx:32: The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in ...
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Section 2 CPU Specified Branch address by @aa:8 (a) Normal Mode * Note: * ZTAT, mask ROM, and ROMless versions only. Figure 2.13 Branch Address Specification in Memory Indirect Mode If an odd address is specified in word or longword ...
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Table 2.6 Effective Address Calculation Addressing Mode and No. Instruction Format 1 Register direct (Rn Register indirect (@ERn Register indirect with displacement @(d:16, ERn) or @(d:32, ERn disp 4 Register indirect ...
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Section 2 CPU Addressing Mode and No. Instruction Format 5 Absolute address @aa:8 op abs @aa:16 op abs @aa:24 op abs @aa:32 op abs 6 Immediate #xx:8/#xx:16/#xx:32 op IMM 7 Program-counter relative @(d:8, PC)/@(d:16, PC) op disp Rev. 4.00 Feb ...
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Addressing Mode and No. Instruction Format 8 Memory indirect @@aa:8 Normal mode * op abs Advanced mode op abs Note: * ZTAT, mask ROM, and ROMless versions only. Effective Address Calculation H'000000 abs ...
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Section 2 CPU 2.8 Processing States 2.8.1 Overview The CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and power-down state. Figure 2.14 shows a diagram of the processing states. Figure 2.15 ...
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End of bus request Bus-released state End of exception handling Exception-handling state RES = high 1 Reset state * From any state except hardware standby mode, a transition to the reset state occurs whenever RES Notes: 1. goes low. A ...
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Section 2 CPU 2.8.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to a reset, interrupt, or trap instruction. The CPU fetches a start address (vector) from the ...
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Reset Exception Handling After the RES pin has gone low and the reset state has been entered, when RES goes high again, reset exception handling starts. The CPU enters the power-on reset state when the NMI pin is high, ...
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Section 2 CPU Normal mode * 1 SP CCR CCR * PC (16 bits) (a) Interrupt control mode 0 Advanced mode SP CCR PC (24 bits) (c) Interrupt control mode 0 Notes: 1. ZTAT, mask ROM, and ROMless versions only. ...
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Program Execution State In this state the CPU executes program instructions in sequence. 2.8.5 Bus-Released State This is a state in which the bus has been released in response to a bus request from a bus master other than ...
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Section 2 CPU 2.9 Basic Timing 2.9.1 Overview The CPU is driven by a system clock, denoted by the symbol . The period from one rising edge of to the next is referred "state." The memory cycle ...
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Bus cycle Address bus Unchanged AS High RD High HWR, LWR High Data bus High-impedance state Figure 2.18 Pin States during On-Chip Memory Access T1 Rev. 4.00 Feb 15, 2006 page 63 of 900 Section 2 CPU REJ09B0291-0400 ...
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Section 2 CPU 2.9.3 On-Chip Supporting Module Access Timing The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16 bits wide, depending on the particular internal I/O register being accessed. Figure 2.19 ...
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Address bus AS RD HWR, LWR Data bus Figure 2.20 Pin States during On-Chip Supporting Module Access 2.9.4 External Address Space Access Timing The external address space is accessed with an 8-bit or 16-bit data bus width in a two-state ...
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Section 2 CPU Rev. 4.00 Feb 15, 2006 page 66 of 900 REJ09B0291-0400 ...
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Section 3 MCU Operating Modes 3.1 Overview 3.1.1 Operating Mode Selection (F-ZTAT™ Version) The H8S/2345 Group has eight operating modes (modes 10, 11, 14 and 15). These modes are determined by the mode pin (MD CPU operating ...
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Section 3 MCU Operating Modes Modes are externally expanded modes that allow access to external memory and peripheral devices. The external expansion modes allow switching between 8-bit and 16-bit bus modes. After program execution starts, an 8-bit ...
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Table 3.2 MCU Operating Mode Selection MCU Operating Mode ...
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Section 3 MCU Operating Modes Table 3.3 MCU Registers Name Mode control register System control register System control register Notes: 1. Lower 16 bits of the address. 2. The SYSCR2 register can only be used in the ...
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System Control Register (SYSCR) Bit : 7 — Initial value : 0 R/W : R/W R/W Bits 7 and 6—Reserved: Only 0 should be written to these bits. Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): ...
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Section 3 MCU Operating Modes 3.2.3 System Control Register 2 (SYSCR2) (F-ZTAT Version Only) Bit : 7 — Initial value : 0 R/W : — SYSCR2 is an 8-bit readable/writable register that performs on-chip flash memory control. SYSCR2 is initialized ...
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Operating Mode Descriptions 3.3.1 Mode 1 (ZTAT, Mask ROM, and ROMless Versions Only) The CPU can access a 64-kbyte address space in normal mode. The on-chip ROM is disabled, and 8-bit bus mode is set, immediately after a reset. ...
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Section 3 MCU Operating Modes The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. However, note that if 8-bit access is designated by the bus controller for all areas, the bus mode switches ...
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Modes 8 and 9 (F-ZTAT Version Only) Modes 8 and 9 are not supported in the H8S/2345 Group, and must not be set. 3.3.9 Mode 10 (F-ZTAT Version Only) This is a flash memory boot mode. For details, see ...
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Section 3 MCU Operating Modes 3.4 Pin Functions in Each Operating Mode The pin functions of ports 1 and vary depending on the operating mode. Table 3.3 shows their functions in each operating mode. Table 3.3 Pin ...
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Memory Map in Each Operating Mode Memory maps for the H8S/2345, H8S/2344, H8S/2343, H8S/2341, and H8S/2340 are shown in figure 3.1 to figure 3.5. The address space is 64 kbytes in modes (normal modes ...
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Section 3 MCU Operating Modes Mode (normal expanded mode with on-chip ROM disabled) H'0000 External address space H'EC00 On-chip RAM * 1 H'FC00 External address space H'FE40 Internal I/O registers H'FF08 External address space H'FF28 Internal I/O ...
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Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 External address space H'FFEC00 On-chip RAM * 3 H'FFFC00 External address space H'FFFE40 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O registers H'FFFFFF Notes: 1. When ...
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Section 3 MCU Operating Modes Mode 10 * (advanced expanded mode with on-chip ROM enabled) H'000000 H'00FFFF H'010000 external address H'01FFFF H'020000 External address H'FFEC00 On-chip RAM * External address H'FFFC00 H'FFFE40 H'FFFF08 External address H'FFFF28 H'FFFFFF Notes: 1. When ...
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Mode User Program Mode (advanced expanded mode with on-chip ROM enabled) H'000000 On-chip ROM H'00FFFF H'010000 On-chip ROM/ external address space * H'01FFFF H'020000 External address space H'FFEC00 On-chip RAM * External address H'FFFC00 space H'FFFE40 Internal ...
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Section 3 MCU Operating Modes Mode 1 (normal expanded mode with on-chip ROM disabled) H'0000 External address space H'EC00 On-chip RAM * H'FC00 External address space H'FE40 Internal I/O registers H'FF08 External address space H'FF28 Internal I/O registers H'FFFF Note: ...
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Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 External address space H'FFEC00 On-chip RAM * 4 External address H'FFFC00 space H'FFFE40 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O registers H'FFFFFF Notes: 1. When ...
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Section 3 MCU Operating Modes Mode 1 (normal expanded mode with on-chip ROM disabled) H'0000 External address space H'EC00 Reserved area * H'F400 On-chip RAM * H'FC00 External address space H'FE40 Internal I/O registers H'FF08 External address space H'FF28 Internal ...
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Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 External address space H'FFEC00 Reserved area * 2 H'FFF400 On-chip RAM * 2 External address H'FFFC00 space H'FFFE40 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O ...
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Section 3 MCU Operating Modes Mode 1 (normal expanded mode with on-chip ROM disabled) H'0000 External address space H'EC00 Reserved area * H'F400 On-chip RAM * H'FC00 External address space H'FE40 Internal I/O registers H'FF08 External address space H'FF28 Internal ...
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Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 External address space H'FFEC00 Reserved area * 2 H'FFF400 On-chip RAM * 2 External address H'FFFC00 space H'FFFE40 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O ...
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Section 3 MCU Operating Modes (normal expanded mode with on-chip ROM disabled) H'0000 External address H'EC00 Reserved area H'F400 H'FC00 External address H'FE40 Internal I/O registers H'FF08 External address H'FF28 Internal I/O registers H'FFFF Note: * External addresses can be ...
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Section 4 Exception Handling 4.1 Overview 4.1.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4.1. If two or ...
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Section 4 Exception Handling 4.1.2 Exception Handling Operation Exceptions originate from various sources. Trap instructions and interrupts are handled as follows: 1. The program counter (PC), condition code register (CCR), and extended register (EXR) are pushed onto the stack. 2. ...
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Table 4.2 Exception Vector Table Exception Source Power-on reset Manual reset Reserved for system use Trace Reserved for system use External interrupt NMI Trap instruction (4 sources) Reserved for system use External interrupt IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 ...
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Section 4 Exception Handling 4.2 Reset 4.2.1 Overview A reset has the highest exception priority. When the RES pin goes low, all processing halts and the H8S/2345 Group enters the reset state. A reset initializes the internal state of the ...
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Reset Sequence The H8S/2345 Group enters the reset state when the RES pin goes low. To ensure that the H8S/2345 Group is reset, hold the RES pin low for at least power-up. To reset the H8S/2345 ...
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Section 4 Exception Handling RES Address bus RD HWR, LWR (1) (3) Reset exception handling vector address ((1) = H'000000, (3) = H'000002) (2) (4) Start address (contents of reset exception handling vector address) (5) ...
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Traces Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. For details of interrupt control modes, see section 5, Interrupt Controller. If ...
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Section 4 Exception Handling 4.4 Interrupts Interrupt exception handling can be requested by nine external sources (NMI, IRQ7 to IRQ0) and 43 internal sources in the on-chip supporting modules. Figure 4.4 classifies the interrupt sources and the number of interrupts ...
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Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The TRAPA instruction fetches a start address from a vector table ...
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Section 4 Exception Handling 4.6 Stack Status after Exception Handling Figure 4.5 shows the stack after completion of trap instruction exception handling and interrupt exception handling. SP CCR CCR * PC (16 bits) (a) Interrupt control mode 0 Note: * ...
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Notes on Use of the Stack When accessing word data or longword data, the H8S/2345 Group assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and ...
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Section 4 Exception Handling Rev. 4.00 Feb 15, 2006 page 100 of 900 REJ09B0291-0400 ...
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Section 5 Interrupt Controller 5.1 Overview 5.1.1 Features The H8S/2345 Group controls interrupts by means of an interrupt controller. The interrupt controller has the following features: Two interrupt control modes Any of two interrupt control modes can be set by ...
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Section 5 Interrupt Controller 5.1.2 Block Diagram A block diagram of the interrupt controller is shown in Figure 5.1. INTM1 INTM0 SYSCR NMIEG NMI input NMI input unit IRQ input unit IRQ input ISCR Internal interrupt request WOVI to TEI ...
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Pin Configuration Table 5.1 summarizes the pins of the interrupt controller. Table 5.1 Interrupt Controller Pins Name Symbol Nonmaskable interrupt NMI IRQ7 to IRQ0 Input External interrupt requests 5.1.4 Register Configuration Table 5.2 summarizes the registers ...
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Section 5 Interrupt Controller 5.2 Register Descriptions 5.2.1 System Control Register (SYSCR) Bit : 7 — Initial value : 0 R/W : R/W R/W SYSCR is an 8-bit readable/writable register that selects the interrupt control mode, and the detected edge ...
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Interrupt Priority Registers (IPRA to IPRK) Bit : 7 — IPR6 Initial value : 0 R/W : — R/W The IPR registers are eleven 8-bit readable/writable registers that set priorities (levels for interrupts ...
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Section 5 Interrupt Controller As shown in table 5.3, multiple interrupts are assigned to one IPR. Setting a value in the range from H'0 to H'7 in the 3-bit groups of bits and sets ...
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IRQ Sense Control Registers H and L (ISCRH, ISCRL) ISCRH Bit : 15 IRQ7SCB IRQ7SCA Initial value : 0 R/W : R/W R/W ISCRL Bit : 7 IRQ3SCB IRQ3SCA Initial value : 0 R/W : R/W R/W The ISCR ...
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Section 5 Interrupt Controller 5.2.5 IRQ Status Register (ISR) Bit : 7 IRQ7F IRQ6F Initial value : 0 R/(W) * R/(W) * R/W : Note: * Only 0 can be written, to clear the flag. ISR is an 8-bit readable/writable ...
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Interrupt Sources Interrupt sources comprise external interrupts (NMI and IRQ7 to IRQ0) and internal interrupts (43 sources). 5.3.1 External Interrupts There are nine external interrupts: NMI and IRQ7 to IRQ0. Of these, NMI and IRQ2 to IRQ0 can be ...
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Section 5 Interrupt Controller Figure 5.3 shows the timing of setting IRQnF. IRQn input pin IRQnF Figure 5.3 Timing of Setting IRQnF The vector numbers for IRQ7 to IRQ0 interrupt exception handling are 23 to 16. Detection of IRQ7 to ...
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Table 5.4 Interrupt Sources, Vector Addresses, and Interrupt Priorities Origin of Interrupt Interrupt Source Source NMI External pin IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 SWDTEND (software DTC activation interrupt end) WOVI (interval timer) Watchdog timer Reserved — ADI ...
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Section 5 Interrupt Controller Origin of Interrupt Interrupt Source Source TGI1A (TGR1A input TPU capture/compare match) channel 1 TGI1B (TGR1B input capture/compare match) TCI1V (overflow 1) TCI1U (underflow 1) TGI2A (TGR2A input TPU capture/compare match) channel 2 TGI2B (TGR2B input ...
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Origin of Interrupt Interrupt Source Source CMIA0 (compare match A0) 8-bit timer channel 0 CMIB0 (compare match B0) OVI0 (overflow 0) Reserved — CMIA1 (compare match A1) 8-bit timer channel 1 CMIB1 (compare match B1) OVI1 (overflow 1) Reserved — ...
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Section 5 Interrupt Controller 5.4 Interrupt Operation 5.4.1 Interrupt Control Modes and Interrupt Operation Interrupt operations in the H8S/2345 Group differ depending on the interrupt control mode. NMI interrupts are accepted at all times except in the reset state and ...
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Figure 5.4 shows a block diagram of the priority decision circuit. Interrupt source Figure 5.4 Block Diagram of Interrupt Control Operation (1) Interrupt Acceptance Control In interrupt control mode 0, interrupt acceptance is controlled by the I bit in CCR. ...
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Section 5 Interrupt Controller (2) 8-Level Control In interrupt control mode 2, 8-level mask level determination is performed for the selected interrupts in interrupt acceptance control according to the interrupt priority level (IPR). The interrupt source selected is the interrupt ...
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Table 5.8 Operations and Control Signal Functions in Each Interrupt Control Mode Interrupt Acceptance Interrupt Setting Control Mode INTM1 INTM0 Legend: : Interrupt operation control performed operation. (All interrupts enabled) IM ...
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Section 5 Interrupt Controller [7] A vector address is generated for the accepted interrupt, and execution of the interrupt handling routine starts at the address indicated by the contents of that vector address. IRQ0 Yes Figure 5.5 Flowchart of Procedure ...
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Interrupt Control Mode 2 Eight-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts by comparing the interrupt mask level set by bits EXR in the CPU with IPR. Figure 5.6 shows a ...
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Section 5 Interrupt Controller Level 7 interrupt? Yes Mask level 6 or below? Yes Figure 5.6 Flowchart of Procedure Up to Interrupt Acceptance in Rev. 4.00 Feb 15, 2006 page 120 of 900 REJ09B0291-0400 Program execution status No Interrupt generated? ...
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Interrupt Exception Handling Sequence Figure 5.7 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip ...
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Section 5 Interrupt Controller Figure 5.7 Interrupt Exception Handling Rev. 4.00 Feb 15, 2006 page 122 of 900 REJ09B0291-0400 ...
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Interrupt Response Times The H8S/2345 Group is capable of fast word transfer instruction to on-chip memory, and the program area is provided in on-chip ROM and the stack area in on-chip RAM, enabling high- speed processing. Table 5.9 shows ...
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Section 5 Interrupt Controller Table 5.10 Number of States in Interrupt Handling Routine Execution Statuses Symbol Instruction fetch Branch address read Stack manipulation Legend: m: Number of wait states in an external device access. 5.5 Usage Notes 5.5.1 Contention between ...
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Internal address bus Internal write signal CMIEA CMFA CMIA interrupt signal Figure 5.8 Contention between Interrupt Generation and Disabling The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt ...
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Section 5 Interrupt Controller 5.5.4 Interrupts during Execution of EEPMOV Instruction Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction. With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer is not accepted until the ...
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Block Diagram Figure 5.9 shows a block diagram of the DTC interrupt controller. Interrupt request IRQ interrupt Interrupt source On-chip clear signal supporting module Interrupt controller Figure 5.9 Interrupt Control for DTC and DMAC 5.6.3 Operation The interrupt controller ...
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Section 5 Interrupt Controller (2) Determination of Priority The DTC activation source is selected in accordance with the default priority order, and is not affected by mask or priority levels. See section 7.3.3, DTC Vector Table, for the respective priorities. ...
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Section 6 Bus Controller 6.1 Overview The H8S/2345 Group has a built-in bus controller (BSC) that manages the external address space divided into eight areas. The bus specifications, such as bus width and number of access states, can be set ...
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Section 6 Bus Controller 6.1.2 Block Diagram Figure 6.1 shows a block diagram of the bus controller. CS0 to CS3 External bus control signals BREQ BACK WAIT Figure 6.1 Block Diagram of Bus Controller Rev. 4.00 Feb 15, 2006 page ...
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Pin Configuration Table 6.1 summarizes the pins of the bus controller. Table 6.1 Bus Controller Pins Name Symbol AS Address strobe RD Read HWR High write LWR Low write CS0 to Chip select CS3 WAIT Wait ...
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Section 6 Bus Controller 6.2 Register Descriptions 6.2.1 Bus Width Control Register (ABWCR) Bit : 7 ABW7 ABW6 Modes Initial value : R/W Mode 4 Initial value : 0 ...
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Access State Control Register (ASTCR) Bit : 7 AST7 AST6 Initial value : 1 R/W : R/W ASTCR is an 8-bit readable/writable register that designates each area as either a 2-state access space or a 3-state access space. ASTCR ...
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Section 6 Bus Controller 6.2.3 Wait Control Registers H and L (WCRH, WCRL) WCRH and WCRL are 8-bit readable/writable registers that select the number of program wait states for each area. In normal mode * , only part of area ...
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Bits 5 and 4—Area 6 Wait Control 1 and 0 (W61, W60): These bits select the number of program wait states when area 6 in external space is accessed while the AST6 bit in ASTCR is set to 1. Bit ...
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Section 6 Bus Controller (2) WCRL Bit : 7 W31 Initial value : 1 R/W : R/W Bits 7 and 6—Area 3 Wait Control 1 and 0 (W31, W30): These bits select the number of program wait states when area ...
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Bits 3 and 2—Area 1 Wait Control 1 and 0 (W11, W10): These bits select the number of program wait states when area 1 in external space is accessed while the AST1 bit in ASTCR is set to 1. Bit ...
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Section 6 Bus Controller Bit 7—Idle Cycle Insert 1 (ICIS1): Selects whether or not one idle cycle state inserted between bus cycles when successive external read cycles are performed in different areas. Bit 7 ICIS1 Description 0 ...
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Bit 3—Burst Cycle Select 0 (BRSTS0): Selects the number of words that can be accessed in a burst ROM interface burst access. Bit 3 BRSTS0 Description 0 Max. 4 words in burst access 1 Max. 8 words in burst access ...
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Section 6 Bus Controller Bit 5 EAE Description 0 Addresses H'010000 to H'01FFFF are in on-chip ROM (in the H8S/2345) Addresses H'010000 to H'017FFF are in on-chip ROM and addresses H'018000 to H'01FFFF are a reserved area (in the H8S/2344) ...
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H'000000 Area 0 (2 Mbytes) H'1FFFFF H'200000 Area 1 (2 Mbytes) H'3FFFFF H'400000 Area 2 (2 Mbytes) H'5FFFFF H'600000 Area 3 (2 Mbytes) H'7FFFFF H'800000 Area 4 (2 Mbytes) H'9FFFFF H'A00000 Area 5 (2 Mbytes) H'BFFFFF H'C00000 Area 6 (2 ...
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Section 6 Bus Controller 6.3.2 Bus Specifications The external space bus specifications consist of three elements: bus width, number of access states, and number of program wait states. The bus width and number of access states for on-chip memory and ...
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Table 6.3 Bus Specifications for Each Area (Basic Bus Interface) ABWCR ASTCR WCRH, WCRL ABWn ASTn Wn1 0 0 — — 6.3.3 Memory Interfaces The H8S/2345 Group memory interfaces comprise a basic ...
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Section 6 Bus Controller Areas external expansion mode, all of areas external space. When area external space is accessed, the CS1 to CS3 pin signals respectively can be output. ...
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Chip Select Signals The H8S/2345 Group can output chip select signals (CS0 to CS3) to areas the signal being driven low when the corresponding external space area is accessed. In normal mode * , only the ...
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Section 6 Bus Controller 6.4 Basic Bus Interface 6.4.1 Overview The basic bus interface enables direct connection of ROM, SRAM, and so on. The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL (see table 6.3). 6.4.2 Data ...
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Access Space: Figure 6.5 illustrates data alignment control for the 16-bit access space. With the 16-bit access space, the upper data bus (D for accesses. The amount of data that can be accessed at one time is one byte ...
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Section 6 Bus Controller 6.4.3 Valid Strobes Table 6.4 shows the data buses used and valid strobes for the access spaces read, the RD signal is valid without discrimination between the upper and lower halves of the data ...
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Basic Timing 8-Bit 2-State Access Space: Figure 6.6 shows the bus timing for an 8-bit 2-state access space. When an 8-bit access space is accessed , the upper half (D The LWR pin is fixed high. Wait states cannot ...
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Section 6 Bus Controller 8-Bit 3-State Access Space: Figure 6.7 shows the bus timing for an 8-bit 3-state access space. When an 8-bit access space is accessed, the upper half (D The LWR pin is fixed high. Wait states can ...
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Access Space: Figures 6.8 to 6.10 show bus timings for a 16-bit 2-state access space. When a 16-bit access space is accessed, the upper half (D the even address, and the lower half (D Wait states cannot be ...
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Section 6 Bus Controller Address bus CSn Read HWR LWR Write Note Figure 6.9 Bus Timing for ...
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Address bus CSn Read HWR LWR Write Note Figure 6.10 Bus Timing for ...
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Section 6 Bus Controller 16-Bit 3-State Access Space: Figures 6.11 to 6.13 show bus timings for a 16-bit 3-state access space. When a 16-bit access space is accessed, the upper half (D the even address, and the lower half (D ...
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Address bus CSn Read HWR LWR Write Note Figure 6.12 Bus Timing for ...
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Section 6 Bus Controller Address bus CSn Read HWR LWR Write Note Figure ...
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Wait Control When accessing external space, the H8S/2345 Group can extend the bus cycle by inserting one or more wait states (T ). There are two ways of inserting wait states: program wait insertion and pin w wait insertion ...
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Section 6 Bus Controller Figure 6.14 shows an example of wait state insertion timing. WAIT Address bus AS RD Read Data bus HWR, LWR Write Data bus indicates the timing of WAIT pin sampling. Note: Figure 6.14 Example of Wait ...
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Burst ROM Interface 6.5.1 Overview With the H8S/2345 Group, external space area 0 can be designated as burst ROM space, and burst ROM interfacing can be performed. The burst ROM space interface enables 16-bit configuration ROM with burst access ...
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Section 6 Bus Controller T 1 Address bus CS0 AS RD Data bus Figure 6.15 (a) Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 1) Rev. 4.00 Feb 15, 2006 page 160 of 900 REJ09B0291-0400 Full access ...
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Address bus CS0 AS RD Data bus Figure 6.15 (b) Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 0) 6.5.3 Wait Control As with the basic bus interface, either program wait insertion or pin wait insertion using ...
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Section 6 Bus Controller 6.6 Idle Cycle 6.6.1 Operation When the H8S/2345 Group accesses external space, it can insert a 1-state idle cycle (T bus cycles in the following two cases: (1) when read accesses between different areas occur consecutively, ...
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Write after Read If an external write occurs after an external read while the ICIS0 bit in BCRH is set idle cycle is inserted at the start of the write cycle. Figure 6.17 shows an example ...
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Section 6 Bus Controller (3) Relationship between Chip Select (CS Depending on the system’s load conditions, the RD signal may lag behind the CS signal. An example is shown in figure 6.18. In this case, with the setting for no ...
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Pin States in Idle Cycle Table 6.5 shows pin states in an idle cycle. Table 6.5 Pin States in Idle Cycle Pins Pin State Contents of next bus cycle High impedance ...
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Section 6 Bus Controller In the event of simultaneous external bus release request and external access request generation, the order of priority is as follows: (High) External bus release > Internal bus master external access (Low) 6.7.3 Pin States in ...
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Transition Timing Figure 6.19 shows the timing for transition to the bus-released state. CPU cycle T 0 Address bus Data bus AS RD HWR, LWR BREQ BACK Low level of BREQ pin is sampled at rise of T [1] ...
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Section 6 Bus Controller 6.7.5 Usage Note When MSTPCR is set to H'FFFF or H'EFFF and a transition is made to sleep mode, the external bus release function halts. Therefore, MSTPCR should not be set to H'FFFF or H'EFFF if ...
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Bus Transfer Timing Even if a bus request is received from a bus master with a higher priority than that of the bus master that has acquired the bus and is currently operating, the bus is not necessarily transferred ...
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Section 6 Bus Controller Rev. 4.00 Feb 15, 2006 page 170 of 900 REJ09B0291-0400 ...
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Section 7 Data Transfer Controller 7.1 Overview The H8S/2345 Group includes a data transfer controller (DTC). The DTC can be activated by an interrupt or software, to transfer data. 7.1.1 Features The features of the DTC are: Transfer possible over ...
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Section 7 Data Transfer Controller 7.1.2 Block Diagram Figure 7.1 shows a block diagram of the DTC. The DTC’s register information is stored in the on-chip RAM * . A 32-bit bus connects the DTC to the on-chip RAM (1 ...
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Register Configuration Table 7.1 summarizes the DTC registers. Table 7.1 DTC Registers Name DTC mode register A DTC mode register B DTC source address register DTC destination address register DTC transfer count register A DTC transfer count register B ...
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Section 7 Data Transfer Controller 7.2 Register Descriptions 7.2.1 DTC Mode Register A (MRA) MRA is an 8-bit register that controls the DTC operating mode. Bit : 7 SM1 Initial value : Unde- Unde- fined — R/W : Bits 7 ...