CY7C43642AV-10AC Cypress Semiconductor Corp, CY7C43642AV-10AC Datasheet - Page 27

• Manufacturer Part Number: CY7C43642AV-10AC
• Description: FIFO Mem Sync Dual Depth/Width Bi-Dir 1K x 36 x 2 120-Pin TQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C43642AV-10AC

• Package: 120TQFP
• Configuration: Dual
• Bus Directional: Bi-Directional
• Density: 72 Kb
• Organization: 1Kx36x2
• Data Bus Width: 36 Bit
• Timing Type: Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 3.3 V
• Operating Temperature: 0 to 70 °C

Document #: 38-06020 Rev. *C
Switching Waveforms
Notes:
49. Retransmit is performed in the same manner for FIFO2.
50. Clocks are free-running in this case. CY standard mode only. Write operation should be prohibited one Write clock cycle before the falling edge of RT1, and
51. The Empty and Full flags may change state during Retransmit as a result of the offset of the Read and Write pointers, but flags will be valid at t
52. For the AEA, AEB, AFA, and AFB flags, two clock cycle are necessary after t
53. The number of 36-/18-/9-bit words written into the FIFO should be less than full depth minus 2/4/8 words between the reset of the FIFO (master or partial) and
EFB/FFA
Timing for Mail2 Register and MBF2 Flag (CY Standard and FWFT Modes)
CLKB
CSB
MBB
ENB
CLKA
MBF2
W/RA
MBA
A
W/RB
B
CSA
ENA
CLKA
CLKB
during the retransmit operation, i.e. when RT1 is LOW and t
the Retransmit setup.
0 35
0–35
FIFO1 Retransmit Timing
ENB
RT1
[29]
[26]
(continued)
t
EN
[49, 50, 51, 52, 53.]
t
RSTS
t
t
t
ENS
t
ENS
ENS
ENS
t
DS
FIFO2 Output Register
W1
t
MDV
RTR
t
t
t
t
ENH
t
DH
ENH
ENH
ENH
t
after the RT1 rising edge.
PMF
t
PMR
RTR
to update these flags.
W1 (Remains valid in Mail2 Register after Read)
t
ENS
t
RSTH
t
ENH
t
PMF
t
RTR
CY7C43642AV
CY7C43662AV
CY7C43682AV
t
DIS
Page 27 of 30
RTR
.