CY7C4282V-10ASC Cypress Semiconductor Corp, CY7C4282V-10ASC Datasheet - Page 9

• Manufacturer Part Number: CY7C4282V-10ASC
• Description: FIFO Mem Sync Dual Depth/Width Uni-Dir 64K x 9 64-Pin TQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C4282V-10ASC

• Package: 64TQFP
• Configuration: Dual
• Bus Directional: Uni-Directional
• Density: 576 Kb
• Organization: 64Kx9
• Data Bus Width: 9 Bit
• Timing Type: Synchronous
• Expansion Type: Depth|Width
• Typical Operating Supply Voltage: 3.3 V
• Operating Temperature: 0 to 70 °C

Switching Waveforms
Programmable Almost Empty Flag Timing
Notes:
17. t
18. PAE offset= n.
19. If a read is performed on this rising edge of the read clock, there will be Empty + (n 1) words in the FIFO when PAE goes LOW
20. If a write is performed on this rising edge of the write clock, there will be Full
21. 64K
22. t
Programmable Almost Full Flag Timing
REN
RCLK
rising RCLK is less than t
and the rising edge of WCLK is less than t
WCLK
WEN
SKEW2
SKEW2
PAE
WCLK
WEN
REN
RCLK
PAF
m words for CY7C4282V, 128K
is the minimum time between a rising WCLK and a rising RCLK edge for PAE to change state during that clock cycle. If the time between the edge of WCLK and the
is the minimum time between a rising RCLK edge and a rising WCLK edge for PAF to change during that clock cycle. If the time between the rising edge of RCLK
t
CLKH
t
CLKH
SKEW2
, then PAE may not change state until the next RCLK.
(continued)
FULL
t
SKEW2
SKEW2
m words for CY4292V.
(M+1)WORDS
IN FIFO
t
[17]
, then PAF may not change state until the next WCLK.
ENS
t
ENS
t
ENH
t
ENH
t
CLKL
t
CLKL
Note
t
PAE
18
Note
9
20
(m 1) words of the FIFO when PAF goes LOW.
t
PAF
t
t
ENS
ENS
t
SKEW2
FULL
N + 1 WORDS
IN FIFO
IN FIFO
t
t
ENS
ENS
[22]
M WORDS
[21]
t
t
ENH
ENH
Note
CY7C4282V
CY7C4292V
t
PAF
19
4282V–13
t
PAE
4282V–12