CY7C109B-20VI Cypress Semiconductor Corp, CY7C109B-20VI Datasheet - Page 4

• Manufacturer Part Number: CY7C109B-20VI
• Description: SRAM Chip Async Single 5V 1M-Bit 128K x 8 20ns 32-Pin SOJ
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C109B-20VI

• Package: 32SOJ
• Timing Type: Asynchronous
• Density: 1 Mb
• Typical Operating Supply Voltage: 5 V
• Address Bus Width: 17 Bit
• Number Of I/o Lines: 8 Bit
• Number Of Ports: 1
• Number Of Words: 128K

Switching Characteristics
Document #: 38-05038 Rev. *A
Read Cycle
t
t
t
t
t
t
t
t
t
t
t
Write Cycle
t
t
t
t
t
t
t
t
t
t
Notes:
Parameter
RC
AA
OHA
ACE
DOE
LZOE
HZOE
LZCE
HZCE
PU
PD
WC
SCE
AW
HA
SA
PWE
SD
HD
LZWE
HZWE
5.
6.
7.
8.
9.
Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
t
At any given temperature and voltage condition, t
The internal write time of the memory is defined by the overlap of CE
and the transition of any of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the
write.
The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
OL
HZOE
/I
OH
, t
and 30-pF load capacitance.
HZCE
[8]
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE
Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CE
CE
CE
Power-Up
CE
Power-Down
Write Cycle Time
CE
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
WE LOW to High Z
, and t
1
1
1
1
1
1
LOW to Data Valid, CE
LOW to Low Z, CE
HIGH to High Z, CE
LOW to Power-Up, CE
HIGH to Power-Down, CE
LOW to Write End, CE
HZWE
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage.
[9]
Description
[7]
[6, 7]
[6, 7]
[5]
Over the Operating Range
2
2
HIGH to Low Z
LOW to High Z
2
2
2
HIGH to Write End
HIGH to
HIGH to Data
HZCE
2
LOW to
is less than t
[7]
[6, 7]
LZCE
1
, t
LOW, CE
HZOE
is less than t
2
HIGH, and WE LOW. CE
Min.
12
12
10
10
10
3
0
3
0
0
0
7
0
3
7C1009B-12
7C109B-12
LZOE
, and t
HZWE
HZWE
and t
Max.
12
12
12
6
6
6
6
is less than t
1
SD
and WE must be LOW and CE
.
LZWE
Min.
15
15
12
12
12
3
0
3
0
0
0
8
0
3
for any given device.
7C1009B-15
7C109B-15
CY7C1009B
2
CY7C109B
Max.
HIGH to initiate a write,
15
15
15
7
7
7
7
Page 4 of 12
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns