CY7C09289-9AI Cypress Semiconductor Corp, CY7C09289-9AI Datasheet - Page 8

• Manufacturer Part Number: CY7C09289-9AI
• Description: SRAM Chip Sync Dual 5V 1M-Bit 64K x 16 20ns/9ns 100-Pin TQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C09289-9AI

• Package: 100TQFP
• Timing Type: Synchronous
• Density: 1 Mb
• Data Rate Architecture: SDR
• Typical Operating Supply Voltage: 5 V
• Number Of I/o Lines: 16 Bit
• Number Of Ports: 2
• Number Of Words: 64K

Switching Waveforms
Read Cycle for Flow-Through Output (FT/PIPE = V
Read Cycle for Pipelined Operation (FT/PIPE = V
Notes:
Document #: 38-06040 Rev. *A
15. OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.
16. ADS = V
17. The output is disabled (high-impedance state) by CE
18. Addresses do not have to be accessed sequentially since ADS = V
ADDRESS
ADDRESS
DATA
DATA
IL
CLK
R/W
CE
CE
OUT
CLK
R/W
CE
CE
OE
, CNTEN and CNTRST = V
OUT
OE
0
1
0
1
t
t
t
t
t
t
SC
SW
SA
SC
SW
SA
A
A
n
n
t
t
t
t
HC
HW
HA
t
t
t
CH2
t
HC
HW
HA
CH1
IH
t
1 Latency
CKLZ
.
t
CD1
t
t
CYC2
CYC1
t
CKLZ
t
CL2
t
0
CL1
=V
IH
A
A
or CE
n+1
n+1
IH
IL
)
[15, 16, 17, 18]
1
)
t
Q
IL
DC
= V
[15, 16, 17, 18]
t
n
constantly loads the address on the rising edge of the CLK. Numbers are for reference only.
CD2
IL
following the next rising edge of the clock.
Q
A
n
A
n+2
n+2
Q
t
OHZ
n+1
t
DC
Q
t
t
t
SC
SC
t
OE
n+1
t
OLZ
OHZ
A
A
n+3
CY7C09279/89
CY7C09379/89
n+3
t
OLZ
Q
t
DC
n+2
t
t
HC
HC
t
OE
t
CKHZ
Page 8 of 18
Q
n+2
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