CY37032VP44-143AC Cypress Semiconductor Corp, CY37032VP44-143AC Datasheet - Page 19

• Manufacturer Part Number: CY37032VP44-143AC
• Description: CPLD Ultra37000 Family 960 Gates 32 Macro Cells 143MHz CMOS Technology 3.3V 44-Pin TQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY37032VP44-143AC

• Package: 44TQFP
• Family Name: Ultra37000
• Device System Gates: 960
• Number Of Macro Cells: 32
• Maximum Propagation Delay Time: 8.5 ns
• Number Of User I/os: 37
• Number Of Logic Blocks/elements: 2
• Typical Operating Supply Voltage: 3.3 V
• Maximum Operating Frequency: 143 MHz
• Number Of Product Terms Per Macro: 16
• Re-programmability Support: Yes
• Operating Temperature: 0 to 70 °C

Document #: 38-03007 Rev. *B
Switching Characteristics
Switching Characteristics
t
t
t
f
Combinatorial Mode Parameters
t
t
t
t
t
Input Register Parameters
t
t
t
t
t
t
Synchronous Clocking Parameters
t
t
t
t
t
t
t
Product Term Clocking Parameters
t
t
t
t
t
t
15]
t
Notes:
16. The following values correspond to the CY37512 and CY37384 devices: t
17. The following values correspond to the CY37192V and CY37256V devices: t
18. The following values correspond to the CY37512V and CY37384V devices: t
S JTAG
H JTAG
CO JTAG
JTAG
PD
PDL
PDLL
EA
ER
WL
WH
IS
IH
ICO
ICOL
CO
S
H
CO2
SCS
SL
HL
COPT
SPT
HPT
ISPT
IHPT
CO2PT
ICS
JTAG Timing Parameters
Pipelined Mode Parameters
Parameter
[13]
[13]
[13, 14, 15]
[13, 14, 15]
[11, 13]
[13]
[14, 15]
[13, 14, 15]
[13, 14, 15]
and for the CY37512 devices: t
[13, 14, 15]
[13]
Parameter
[13]
[13, 14, 15]
[13, 14, 15]
[13, 14, 15]
[13, 14,
200 MHz
2.5
2.5
7.5
2.5
2.5
2
2
4
0
5
0
0
6
5
Set-up Time from TDI and TMS to TCK
Hold Time on TDI and TMS
Falling Edge of TCK to TDO
Maximum JTAG Tap Controller Frequency
9.5
12
12
12
11
11
6
8
8
4
7
167 MHz 154 MHz
2.5
2.5
7.5
2.5
2.5
6.5
S
2
2
4
0
6
0
0
6
= 7 ns.
12.5
13.5
6.5
8.5
8.5
Over the Operating Range
12
10
10
14
Over the Operating Range
11
4
2.5
2.5
6.5
8.5
2.5
2.5
6.5
2
2
5
0
0
0
6
14.5
15.5
7.5
4.5
11
12
11
10
15
11
11
[5]
[5]
143 MHz
2.5
2.5
7.5
2
2
5
0
7
9
0
3
3
0
7
12.5
8.5
16
17
13
13
14
12
13
19
6
[12]
[5]
[12]
CO
5.5
8
8
[5]
CO
CO
Description
= 5 ns, t
(continued)
10
[16]
[16]
125 MHz
3
3
2
2
0
0
5
5
0
9
[16]
= 6 ns, t
= 6.5 ns, t
6.5
S
16.5
17.5
12.5
= 6.5 ns, t
10
14
14
16
14
13
19
S
[16]
= 7 ns, f
S
= 9.5 ns, and f
6
SCS
2.5
2.5
5.5
5.5
10
12
10
11
MAX2
[17]
100 MHz
3
3
0
0
0
= 8.5 ns, t
= 143 MHz, f
Ultra37000 CPLD Family
MAX2
6.5
12
17
18
16
16
16
18
16
13
21
[17]
ICS
= 105 MHz.
= 8.5 ns, f
MAX3
8
12
15
14
12
83 MHz
[18]
4
4
3
3
0
0
6
6
0
= 77 MHz, and f
MAX1
8
15
19
20
19
19
19
21
19
15
24
[18]
= 118 MHz.
10
15
15
19
15
66 MHz
5
5
4
4
0
0
7
7
0
MAX4
Page 19 of 63
= 100 MHz;
20
22
24
24
24
24
26
10
24
20
30
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns