DAC1230LCJ-1 National Semiconductor, DAC1230LCJ-1 Datasheet - Page 7

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DAC1230LCJ-1

Manufacturer Part Number
DAC1230LCJ-1
Description
DAC 1-CH R-2R 12-Bit 20-Pin CDIP
Manufacturer
National Semiconductor
Datasheet

Specifications of DAC1230LCJ-1

Package
20CDIP
Resolution
12 Bit
Architecture
R-2R
Digital Interface Type
Parallel
Number Of Outputs Per Chip
1
Output Type
Current
Full Scale Error
-0.2 %FSR
Integral Nonlinearity Error
±0.018 %FSR
Maximum Settling Time
1(Typ) us
Case
DIP-20L

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Application Hints
1 1 Automatic Transfer
The 12-bit DAC word is automatically transferred to the DAC register and the R-2R ladder when the second write (the 4 LSBs of
the data) occurs
1 2 Independent Processor Transfer Control
In this case a separate address is decoded to provide the XFER signal This allows the processor to load the next required DAC
word but not change the analog output until some time later most useful for the simultaneous updating of several DACs in a
system where their XFER lines would be tied together
1 3 Transfer via an External Strobe
This method is basically the same as the previous operation except the XFER signal is provided by a device other than the
processor This allows the DAC to hold the code for a conditional analog output signal which will be required on demand from an
external monitoring device (an analog voltage comparator for instance)
WR2 tied to a logic low (0V)
(Continued)
7
TL H 5690 – 7
TL H 5690– 8
TL H 5690– 9

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