MT4C4M4A1TG-5 Micron Technology Inc, MT4C4M4A1TG-5 Datasheet - Page 18

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MT4C4M4A1TG-5

Manufacturer Part Number
MT4C4M4A1TG-5
Description
DRAM Chip FPM 16M-Bit 4Mx4 5V 24-Pin TSOP Tray
Manufacturer
Micron Technology Inc
Type
FPMr
Datasheet

Specifications of MT4C4M4A1TG-5

Package
24TSOP
Density
16 Mb
Address Bus Width
12 Bit
Operating Supply Voltage
5 V
Maximum Random Access Time
50 ns
Operating Temperature
0 to 70 °C
TIMING PARAMETERS
NOTE: 1. Once
4 Meg x 4 FPM DRAM
D49_5V.p65 – Rev. 5/00
SYMBOL
t
t
t
t
t
CHD
CP
CSR
RASS
RP
RAS#
CAS#
WE#
2. Once
Q
V
V
V
V
V
V
IH
IL
IH
IL
IH
IL
MIN
100
15
30
8
5
t
t
RASS (MIN) is met and RAS# remains LOW, the DRAM will enter self refresh mode.
RPS is satisfied, a complete burst of all rows should be executed if RAS#-only or burst CBR refresh is used.
-5
MAX
t RPC
t CP
t RP
t CSR
t WRP
MIN
100
15
10
40
5
(Addresses and OE# = DON’T CARE)
t WRH
-6
t CHR
MAX
SELF REFRESH CYCLE
t RAS
UNITS
ns
ns
ns
µs
ns
18
t RPC
OPEN
SYMBOL
t
t
t
t
RPC
RPS
WRH
WRP
t RP
t CSR
t WRP
Micron Technology, Inc., reserves the right to change products or specifications without notice.
MIN
t WRH
90
5
8
8
t CHR
-5
t RAS
MAX
MIN
105
10
10
5
FPM DRAM
4 MEG x 4
-6
DON’T CARE
UNDEFINED
©2000, Micron Technology, Inc.
OBSOLETE
MAX
UNITS
ns
ns
ns
ns

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