CS4331-KS Cirrus Logic Inc, CS4331-KS Datasheet - Page 16

• Manufacturer Part Number: CS4331-KS
• Description: DAC 2-CH Delta-Sigma 18-Bit 8-Pin SOIC
• Manufacturer: Cirrus Logic Inc

Specifications of CS4331-KS

• Package: 8SOIC
• Resolution: 18 Bit
• Conversion Rate: 50 KSPS
• Architecture: Delta-Sigma
• Digital Interface Type: Serial
• Number Of Outputs Per Chip: 2
• Output Type: Voltage
• Full Scale Error: ±10 %FSR

Configuration Register
The CS4330, CS4331, CS4333 support multiple
2’s-complement data/clock formats. The required
format is governed by the contents of the Con-
figuration Register. The 5-bit register determines
which serial data format is acceptable, the fre-
quency of the Internal Serial Clock, on which
edge of SCLK audio data must be valid, and the
number of bits to be loaded into the input buffer.
On initial power-up, the register is loaded with
the default settings, and it is not necessary to
write to the register if this format is appropriate.
The default settings are shown in Figures 4-7.
The 8-bit code includes a 3-bit preamble to pre-
vent accidental access to the Configuration
Register. Each bit of the code is read on the fall-
ing edge of LRCK as shown in the Figures 21
and 22. The code 01000000 is considered to be
an error condition and is ignored. The configura-
tion routine requires that the SDATA pin is held
high, as shown in Figures 21 and 22, to prevent
accidental writing to the register. The Configura-
tion Register is only accessible prior to entering
the External Serial Clock Mode. For I
the user must set B6 to 0, and B7 to 1.
16
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2
S mode,
* The Internal SCLK will be 48 Fs, if the
MCLK/LRCK ratio is 384
Selects Data Sampling edge of SCLK
Sets Internal SCLK/LRCK Ratio *
All other Codes
B1
B1
B4
B4
B6
B7
B8
0
0
0
1
1
1
1
0
1
0
1
0
1
B2
B5
B5
B2
1
0
1
0
1
0
1
B3
B3
0
CS4330, CS4331, CS4333
B4
Configuration Access Code
Access Allowed
Access Denied
Internal SCLK Mode only
SCLK/LRCK = 32
Reserved
SCLK/LRCK = 64
SCLK/LRCK = 128
External SCLK Mode only
Rising edge of SCLK
Falling edge of SCLK
Left or Right Justified Data
in relation to LRCK transition
Left Justified
Right Justified
I
Disabled
Enabled
Sets the number of Bits
18 Bits
16 Bits
2
S Data Format
B5
B6
B7
DS136F1
B8