GT28F160C3TA90 Intel, GT28F160C3TA90 Datasheet - Page 18

• Manufacturer Part Number: GT28F160C3TA90
• Description: Flash Mem Parallel 3V/3.3V 16M-Bit 1M x 16 90ns 48-Pin UBGA
• Manufacturer: Intel

Specifications of GT28F160C3TA90

• Package: 48UBGA
• Density: 16 Mb
• Architecture: Sectored
• Block Organization: Asymmetrical
• Location Of Boot Block: Top
• Typical Operating Supply Voltage: 3|3.3 V
• Sector Size: 8KByte x 8|64KByte x 31
• Support Of Common Flash Interface: Yes
• Timing Type: Asynchronous
• Operating Temperature: -40 to 85 °C
• Interface Type: Parallel

Intel
3.1.4
3.1.5
18
£
Advanced+ Boot Block Flash Memory (C3)
Standby
Deselecting the device by bringing CE# to a logic - high level (V
mode, which substantially reduces device power consumption without any latency for subsequent
read accesses. In standby, outputs are placed in a high-impedance state independent of OE#. If
deselected during a Program or Erase operation, the device continues to consume active power
until the Program or Erase operation is complete.
Reset
From read mode, RP# at V
impedance state, and turns off all internal circuits. After return from reset, a time t
until the initial read-access outputs are valid. A delay (t
reset before a write cycle can be initiated. After this wake - up interval, normal operation is restored.
The CUI resets to read-array mode, the status register is set to 0x80, and all blocks are locked. See
Figure 10, “Reset Operations Waveforms” on page
If RP# is taken low for time t
aborted and the memory contents at the aborted location (for a program) or block (for an erase) are
no longer valid, since the data may be partially erased or written. The abort process goes through
the following sequence:
1. When RP# goes low, the device shuts down the operation in progress, a process which takes time
t
2. After time t
enter reset mode (if RP# is deasserted after t
on page
In both cases, after returning from an aborted operation, the relevant time t
must be observed before a Read or Write operation is initiated, as discussed in the previous
paragraph. However, in this case, these delays are referenced to the end of t
RP# goes high.
As with any automated device, it is important to assert RP# during a system reset. When the system
comes out of reset, the processor expects to read from the flash memory. Automated flash
memories provide status information when read during program or Block-Erase operations. If a
CPU reset occurs with no flash memory reset, proper CPU initialization may not occur because the
flash memory may be providing status information instead of array data. Intel
allow proper CPU initialization following a system reset through the use of the RP# input. In this
application, RP# is controlled by the same RESET# signal that resets the system CPU.
PLRH
to complete.
48.
PLRH
, the part will either reset to read-array mode (if RP# is asserted during t
IL
PLPH
for time t
during a Program or Erase operation, the operation will be
PLPH
deselects the memory, places output drivers in a high -
PLRH
). See
48.
PHWL
Figure 10, “Reset Operations Waveforms”
or t
IH
PHEL
) places the device in standby
) is required after return from
PHQV
PLRH
®
Flash memories
or t
rather than when
PHQV
PHWL
Datasheet
is required
PLRH
/t
PHEL
) or