MAX110BCPE Maxim Integrated Products, MAX110BCPE Datasheet - Page 15

• Manufacturer Part Number: MAX110BCPE
• Description: ADC Single Delta-Sigma 0.05KSPS 14-Bit Serial 16-Pin PDIP N
• Manufacturer: Maxim Integrated Products

Specifications of MAX110BCPE

• Package: 16PDIP N
• Resolution: 14 Bit
• Sampling Rate: 50 SPS
• Architecture: Delta-Sigma
• Number Of Adcs: 1
• Number Of Analog Inputs: 2
• Differential Input: Yes
• Digital Interface Type: Serial (SPI, QSPI, Microwire)
• Input Type: Voltage
• Polarity Of Input Voltage: Bipolar

NO-OP is a zero, the control word is not transferred to
the control register, the ADC’s configuration remains
unchanged, and no new conversion is initiated. This
allows specific ADCs in a “daisy chain” arrangement to
be reconfigured while leaving the remaining ADCs
unchanged. Table 1 lists the various ADC control word
functions.
Output data is shifted out of DOUT at the same time the
input control word for the next conversion is shifted in
(Figure 8).
On power-up, all internal registers reset to zero.
Therefore, when writing the first control word to the
ADC, the data simultaneously shifted out will be zeros.
The first conversion begins when CS goes high (NO-OP
= 1). The results are placed in the 16-bit I/O register for
access on the next data-transfer operation.
Bits 0 and 1 control the ADC’s power-down mode. If bit
0 (PD) is a logic high, power is removed from all analog
circuitry except the RC oscillator. A logic high at bit 1
(PDX) removes power from the RC oscillator. If both bits
PD and PDX are a logic high, or if PD is high and
RCSEL is low, the supply currents reduce to 4µA. If an
external XCLK clock continues to run in power-down
mode, the supply current will depend on the clock rate.
Table 1. Input Control-Word Bit Map
NO-OP
5, 6, 13, 14
15
First bit clocked in.
9–12
BIT
7, 8
15
4
3
2
1
0
NU
14
Low-Cost, 2-Channel, ±14-Bit Serial ADCs
CONV1–CONV4
NU
13
______________________________________________________________________________________
DV2, DV4
NO-OP
NAME
CHS
CAL
NUL
PDX
NU
PD
CONV4
12
CONV3
11
Power-Down Mode
If this bit is a logic high, the remaining 15 LSBs are transferred to the control register and a
new conversion begins when CS returns high. If this bit is set low, the control word is not
passed to the control register, the ADC configuration remains unchanged, and no new con-
version begins when CS returns high.
Used for test purposes only. Set these bits low.
Conversion Time Control Bits. See Table 4.
XCLK to Oversampling Cock Ratio Control Bits. See Table 5.
Input Channel Select. A logic high selects channel 2 (IN2+ and IN2-), while a logic low
selects channel 1 (IN1+ and IN1-). See Tables 2 and 3.
Gain-Calibration Bit. A logic high selects gain-calibration mode. See Table 3.
Internal Offset-Null Bit. A logic high selects offset-null mode. See Table 3.
Oscillator Power-Down. Set this bit high to power down the RC oscillator.
Analog Power-Down. Set this bit high to power down the analog section.
CONV2
10
CONV1
9
DV4
8
DV2
When PDX is set high, the internal RC oscillator stops
shortly after CS returns high. If the next control word
written to the device has NO-OP = 1 instructing the
ADC to convert, BUSY will go low, but because the RC
oscillator is stopped, BUSY will remain low and will not
allow a new conversion to begin. To avoid this situation,
write a “dummy” control word with NO-OP = 0 and any
combination of bits 14-0 in the control word following
the control word with PDX = 0. With NO-OP = 0, bits 14-
0 are ignored and the internal state machine resets.
Next, perform a normal 3-step calibration (see Table 3).
Note that XCLK must be connected to V
through a resistor (suggested value is 1MΩ) when the
RC oscillator mode is selected (RCSEL = V
resistor is not necessary if the external oscillator mode
is used, or if the internal oscillator is not shut down.
Bit 4 (CHS) controls which of the two differential inputs
connect to the internal ADC inputs (see the Functional
Diagram ). A logic high selects IN2+ and IN2- while a
logic low selects IN1+ and IN1-. Table 2 shows the
allowable input multiplexer configurations.
7
NU
DESCRIPTION
6
NU
5
Selecting the Analog Inputs
CHS
4
CAL
3
NUL
2
PDX
DD
1
DD
or GND
). This
PD
0
15