GAL20V8C-5LJ Lattice, GAL20V8C-5LJ Datasheet - Page 9

• Manufacturer Part Number: GAL20V8C-5LJ
• Description: SPLD GAL Family 8 Macro Cells 166MHz EECMOS Technology 5V 28-Pin PLCC
• Manufacturer: Lattice

Specifications of GAL20V8C-5LJ

• Package: 28PLCC
• Family Name: GAL
• Maximum Propagation Delay Time: 5 ns
• Typical Operating Supply Voltage: 5 V
• Maximum Internal Frequency: 166 MHz
• Number Of Product Terms Per Macro: 8
• Re-programmability Support: Yes

In the Complex mode, macrocells are configured as output only or
I/O functions.
Architecture configurations available in this mode are similar to the
common 20L8 and 20P8 devices with programmable polarity in
each macrocell.
Up to six I/Os are possible in this mode. Dedicated inputs or outputs
can be implemented as subsets of the I/O function. The two outer
most macrocells (pins 15 & 22) do not have input capability. De-
Note: The development software configures all of the architecture control bits and checks for proper pin usage automatically.
Complex Mode
XOR
XOR
7
signs requiring eight I/Os can be implemented in the Registered
mode.
All macrocells have seven product terms per output. One product
term is used for programmable output enable control. Pins 1 and
13 are always available as data inputs into the AND array.
The JEDEC fuse numbers including the UES fuses and PTD fuses
are shown on the logic diagram on the following page.
Combinatorial I/O Configuration for Complex Mode
Combinatorial Output Configuration for Complex Mode
- SYN=1.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=1.
- Pin 16 through Pin 21 are configured to this function.
- SYN=1.
- AC0=1.
- XOR=0 defines Active Low Output.
- XOR=1 defines Active High Output.
- AC1=1.
- Pin 15 and Pin 22 are configured to this function.
Specifications GAL20V8