HN58V66AFP-10 Renesas Electronics America, HN58V66AFP-10 Datasheet - Page 22

• Manufacturer Part Number: HN58V66AFP-10
• Description: EEPROM Parallel 64K-Bit 8K x 8 3.3V/5V 28-Pin SOP
• Manufacturer: Renesas Electronics America

Specifications of HN58V66AFP-10

• Package: 28SOP
• Interface Type: Parallel
• Density: 64 Kb
• Maximum Random Access Time: 100 ns
• Typical Operating Supply Voltage: 3.3|5 V
• Organization: 8Kx8
• Data Retention: 10(Min) Year
• Hardware Data Protection: Yes
• Operating Temperature: 0 to 70 °C

HN58V65A Series, HN58V66A Series
Functional Description
Automatic Page Write
Page-mode write feature allows 1 to 64 bytes of data to be written into the EEPROM in a single write
cycle. Following the initial byte cycle, an additional 1 to 63 bytes can be written in the same manner. Each
additional byte load cycle must be started within 30 s from the preceding falling edge of WE or CE.
When CE or WE is kept high for 100 µs after data input, the EEPROM enters write mode automatically
and the input data are written into the EEPROM.
Data Polling
Data
Data polling indicates the status that the EEPROM is in a write cycle or not. If EEPROM is set to read
mode during a write cycle, an inversion of the last byte of data outputs from I/O7 to indicate that the
EEPROM is performing a write operation.
RDY/Busy
RDY/Busy signal also allows status of the EEPROM to be determined. The RDY/Busy signal has high
impedance except in write cycle and is lowered to V
cycle, the RDY/Busy signal changes state to high impedance.
RES Signal (only the HN58V66A series)
RES
When RES is low, the EEPROM cannot be read or programmed. Therefore, data can be protected by
keeping RES low when V
doesn’t provide a latch function.
Data
Data
RES
RES
Rev.3.00, Dec. 04.2003, page 20 of 26
Busy
Busy Signal
Busy
V
4-5
CC
CC
is switched. RES should be high during read and programming because it
Program inhibit
Read inhibit
OL
Read inhibit
Program inhibit
after the first write signal. At the end of a write