A25L010M-F AMIC, A25L010M-F Datasheet
A25L010M-F
Specifications of A25L010M-F
Related parts for A25L010M-F
A25L010M-F Summary of contents
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... Version 1.6) A25L020/A25L010/A25L512 Series 2Mbit / 1Mbit / 512Kbit Low Voltage, Serial Flash Memory for 33MHz CC3 to 25μA CC2 With 100MHz Uniform 4KB Sectors Issue Date February 27, 2008 September 2, 2008 January 9, 2009 April 30, 2010 October 20, 2010 December 23, 2010 AMIC Technology Corp. Remark Final ...
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... The whole memory can be erased using the Chip Erase instruction, a block at a time, using Block Erase instruction sector at a time, using the Sector Erase instruction HOLD DIO 1 With 100MHz Uniform 4KB Sectors pages, or DIP8 Connections A25L020/ A25L010/ A25L512 HOLD DIO SS AMIC Technology Corp. 262,144/131,072/ ...
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... HOLD C DIO High Voltage Generator I/O Shift Register 256 Byte Data Buffer 3FFFFh (2M), 1FFFFh (1M) FFFFh (512K) 00000h 256 Byte (Page Size) X Decoder 2 A25L020/A25L010/A25L512 Series USON8 Connections A25L020/ A25L010/ A25L512 HOLD DIO SS Status Register Size of the memory area 000FFh AMIC Technology Corp. ...
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... A25L020/A25L010/A25L512 Series Logic Symbol V CC DIO C A25L020/ S A25L010/ A25L512 W HOLD Low enables the device, placing The Hold ( HOLD ) signal is used to pause HOLD serial communications with ). The main purpose of this input signal is W AMIC Technology Corp required the device without S ) driven Low. ...
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... C remains at 0 for (CPOL=0, CPHA=0) – C remains at 1 for (CPOL=1, CPHA= DIO SPI Memory Device S W HOLD HOLD ) signals should be driven, High or Low as appropriate MSB DO 4 A25L020/A25L010/A25L512 Series C DO DIO C DO SPI Memory SPI Memory Device S W HOLD S MSB AMIC Technology Corp. DIO Device W HOLD ...
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... Deep Power-down mode offers extra software protection from inadvertent Write, Program and Erase instructions, as all instructions are ignored except one particular instruction (the instruction signal. boasts the following data ) can provide PUW W ) signal allows the Block Protect Release from Deep Power-down AMIC Technology Corp. ...
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... Protected Area None All block All block 6 Memory Content Unprotected Area 1 All blocks Lower 3/4ths (3 blocks Lower half (2 blocks None Memory Content Unprotected Area 1 All blocks Lower half (1 blocks: 0) None Memory Content Unprotected Area 1 All block None None AMIC Technology Corp. ...
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... To restart communication with the device necessary to drive Hold ( Chip Select ( S ) Low. This prevents the device from going back to the Hold condition. Hold Hold Condition Condition (standard use) (non-standard use HOLD ) High, and then to drive AMIC Technology Corp. ...
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... Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector, Block, or Chip Erasable (bits are erased from but not Page Erasable. Address Range 1F000h 10000h 0F000h 03000h 02000h 01000h 00000h AMIC Technology Corp. 8 3FFFFh 30FFFh 2FFFFh 20FFFh 1FFFFh 10FFFh 0FFFFh 03FFFh 02FFFh ...
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... A25L020/A25L010/A25L512 Series Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector, Block, or Chip Erasable (bits are erased from but not Page Erasable. Address Range F000h 3000h 2000h 1000h 0000h AMIC Technology Corp. 9 FFFFh 3FFFh 2FFFh 1FFFh 0FFFh ...
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... A25L020/A25L010/A25L512 Series One-byte Address Dummy Bytes 06h 0 04h 0 05h 0 01h 0 03h 3 0Bh 3 3Bh 3 (2) BBh 3 02h 3 20h 3 D8h 3 C7h 0 B9h 0 9Fh 0 (3) 90h 1 0 ABh 0 AMIC Technology Corp must be driven S ) must Data Bytes Bytes ∞ ∞ ∞ ∞ ( ∞ 256 ∞ ∞ ∞ ...
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... Write Disable (WRDI) instruction completion ﹣ Write Status Register (WRSR) instruction completion ﹣ Page Program (PP) instruction completion ﹣ Sector Erase (SE) instruction completion ﹣ Bulk Erase (BE) instruction completion Instruction DIO High Impedance Low, sending the instruction code, and then S ) High AMIC Technology Corp. ...
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... Register (SRWD, BP2, BP1, BP0) become read-only bits and the Write Status Register (WRSR) instruction is no longer accepted for execution Status Register Out MSB 12 A25L020/A25L010/A25L512 Series W ) signal allow the device to be put in the Status Register Out MSB AMIC Technology Corp signal ...
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... Hardware Protected Mode (HPM). The Write Status Register (WRSR) instruction is not executed once the Hardware Protected Mode (HPM) is entered initiated. While the Instruction 7 High Impedance MSB 13 A25L020/A25L010/A25L512 Series Status Register AMIC Technology Corp. ) signal. The Status W ) ...
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... Block Erase, and Chip and Block Erase Erase instructions Protected against Page Ready to accept Page Program, Sector Erase, Program, Sector Erase, Block Erase, and Chip and Block Erase Erase instructions W ) Low W ) Low after setting the permanently tied High, the Hardware AMIC Technology Corp High. ...
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... High at any time during data output. Any Read Data Bytes (READ) instruction, while an Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress 24-Bit Address MSB High. Chip Select ( 0 Data Out 2 Data Out MSB AMIC Technology Corp. ) can be driven ...
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... Erase, Program or Write cycle is in progress, is rejected without having any effects on the cycle that is in progress Instruction 24-Bit Address MSB Data Out MSB 16 A25L020/A25L010/A25L512 Series S ) can be driven High at any time during data Data Out MSB AMIC Technology Corp High. 7 MSB ...
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... However, the DIO pin should be high-impedance prior to the falling edge of the first data out clock. This Instruction 24-Bit Address MSB DIO switches from input to output MSB Data Out 1 Data Out 2 17 A25L020/A25L010/A25L512 Series MSB Data Out 3 Data Out 4 AMIC Technology Corp. 7 MSB ...
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... Instruction 24-Bit Address MSB DIO switches from input to output MSB MSB Data Out 2 Data Out 3 Data Out 1 18 A25L020/A25L010/A25L512 Series of f (See AC Characteristics MSB Data Out 4 Data Out 5 AMIC Technology Corp. This is 7 MSB ...
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... Instruction 24-Bit Address MSB Data Byte MSB 19 A25L020/A25L010/A25L512 Series S ) must be driven High after the eighth bit of the driven High, the self-timed Data Byte MSB Data Byte 256 MSB AMIC Technology Corp initiated. While PP ...
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... Write Enable Latch (WEL) bit is reset. A Sector Erase (SE) instruction applied to a page which is protected by the Block Protect (BP2, BP1, BP0) bits (see table 1, table 2, table 3 and table 4.) is not executed Instruction 24-Bit Address MSB initiated. While the Sector Erase cycle AMIC Technology Corp ...
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... A Block Erase (BE) instruction applied to a page which is protected by the Block Protect (BP2, BP1, BP0) bits (see table 1, table 2, table 3 and table 4.) is not executed Instruction MSB 21 A25L020/A25L010/A25L512 Series ) is initiated. While the Block Erase cycle is in progress 24-Bit Address AMIC Technology Corp ...
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... At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset. The Chip Erase (CE) instruction is executed only if all Block Protect (BP2, BP1, BP0) bits are 0. The Chip Erase (CE) instruction is ignored if one, or more, blocks are protected Instruction driven High AMIC Technology Corp. ...
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... Instruction Stand-by Mode 23 A25L020/A25L010/A25L512 Series S ) Low, followed by the instruction code must be driven Low S ) must be driven High after the eighth bit of the driven High, it requires a delay Deep Power-down Mode AMIC Technology Corp. DP and the Deep CC2 ...
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... Low. and execute instructions. Device Identification Memory Type 30h Manufacture ID Memory Type High at any time during data output driven High, the device is put in the Memory Capacity 12h (A25L020) 11h (A25L010) 10h (A25L512 Memory Capacity AMIC Technology Corp. ...
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... The manufacturer identification is assigned by JEDEC, and has the value 37h for AMIC. The device identification is assigned by the device manufacturer. Any Read Electronic Manufacturer ID & Device ID (REMS) instruction while an Erase, or Program cycle is in progress, is not decoded, and has no effect on the cycle that is in progress ...
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... Dummy Bytes MSB MSB Deep Power-down Mode 26 ) High after the Electronic Signature has been read driven Low, cause the driven High, the device is put in the , and Chip Select ( RES2 (max), as specified in AC RES2 t RES2 Stand-by Mode AMIC Technology Corp ...
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... Stand-by Power mode is delayed by t and Chip Select ( as specified in AC Characteristics Table. Once in the Stand-by Power mode, the device waits to be selected, so that it can receive, decode and execute instructions. 27 RES1 Stand-by Mode S ) must remain High for at least t AMIC Technology Corp. , RES1 (max), RES1 ...
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... The device is in the Standby mode (not the Deep Power-down mode). The Write Enable Latch (WEL) bit is reset. feed. Each device in a system should CC rail decoupled by a suitable capacitor close to CC drops from the operating voltage, CC Full Device Access time AMIC Technology Corp. has risen above CC , all operations are WI ...
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... INITIAL DELIVERY STATE The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0). (December, 2010, Version 1.6) A25L020/A25L010/A25L512 Series Parameter 29 Min. Max. Unit 2 AMIC Technology Corp. ...
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... Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the AMIC SURE Program and other relevant quality docu- ments. Measurement Conditions summarized in the relevant tables. Designers should check that the operating conditions in their ...
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... DO = open 1.6mA –100µA OH Parameter Parameter 31 Min. Max –0.5 0.3V 0. –0.2 CC Min. Typ. Max 0.2 0.24 0.5 1 2.5 0.5 1.3 Min. Max 0. 0. AMIC Technology Corp. Unit ± 2 µA ± 2 µA 25 µA 25 µ +0 Unit Unit ...
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... Figure 22. AC Measurement I/O Waveform 0.8V 0.2V (December, 2010, Version 1.6) A25L020/A25L010/A25L512 Series Input Levels Input and Output Timing Reference Levels 0.7V CC 0.5V CC 0.3V CC AMIC Technology Corp. ...
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... Only applicable as a constraint for a WRSR instruction when SRWD is set at 1. (December, 2010, Version 1.6) A25L020/A25L010/A25L512 Series Parameter 3 (peak to peak) 3 (peak to peak Min. Typ. Max. Unit D.C. 100 MHz D.C. 50 MHz 0.1 V/ns 0.1 V/ 100 100 ns 3 µs 30 µs 30 µ 0.2 0.24 s 0.5 1 2.5 s 0.5 1.3 s AMIC Technology Corp. ...
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... Figure 23. Serial Input Timing S tCHSL C tDVCH DIO DO Figure 24. Write Protect Setup and Hold Timing during WRSR when SRWD=1 W tWHSL S C DIO DO (December, 2010, Version 1.6) tSLCH tCHDX MSB IN High Impedance High Impedance 34 A25L020/A25L010/A25L512 Series tSHSL tSHCH tCHSH tCHCL tCLCH LSB IN tSHWL AMIC Technology Corp. ...
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... Figure 25. Hold Timing S C DIO DO HOLD Figure 26. Output Timing S C DIO ADDR.LSB IN tCLQV tCLQX tCLQX DO (December, 2010, Version 1.6) A25L020/A25L010/A25L512 Series tHLCH tCHHL tCHHH tHLQZ tCH tCLQV 35 tHHCH tHHQX tCL LSB OUT tQLQH tQHQL AMIC Technology Corp. tSHQZ ...
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... Mbit (4KB uniform sectors) 020 = 2 Mbit (4KB uniform sectors) 040 = 4 Mbit (4KB uniform sectors) 080 = 8 Mbit (4KB uniform sectors) 016 = 16 Mbit (4KB uniform sectors) 032 = 32 Mbit (4KB uniform sectors) Device Voltage L = 2.7-3.6V Device Type A25 = AMIC Serial Flash AMIC Technology Corp. ...
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... C ~ +85 ° C Blank is for commercial temperature range: 0 ° +70 ° C Part No. Speed (MHz) A25L010-F A25L010-UF A25L010O-F A25L010O-UF A25L010M-F 100 A25L010M-UF A25L010V-F A25L010V-UF A25L010Q1 for industrial operating temperature range: -40°C ~ +85°C Blank is for commercial temperature range: 0 ° +70 ° C (December, 2010, Version 1 ...
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... Pin Pb-Free DIP (300 mil) 8 Pin Pb-Free SOP (150 mil) 8 Pin Pb-Free SOP (150 mil) 8 Pb-Free Pin SOP (209mil Pb-Free Pin SOP (209mil) 8 Pin Pb-Free TSSOP 8 Pin Pb-Free TSSOP 8 Pin Pb-Free USON (2*3mm) Operating temperature range: -40°C ~ +85°C AMIC Technology Corp. ...
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... Dimensions in mm Min Nom Max - - 4.57 0. 3.25 3.30 3.45 0.36 0.46 0.56 1.27 1.52 1.78 0.81 0.99 1.17 0.20 0.25 0.33 8.89 9.14 9.40 7.37 7.62 8.00 6.45 6.60 6.76 - 2. 8.76 - 9.78 0.41 0.53 0.66 AMIC Technology Corp. unit: inches/mm ...
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... Dimensions in mm Symbol A 1.35~1.75 A 0.10~0. 0.33~0.51 D 4.7~5.0 E 3.80~4.00 e 1.27 BSC H 5.80~6. 0.40~1.27 Notes: 1. Maximum allowable mold flash is 0.15mm. 2. Complies with JEDEC publication 95 MS –012 AA. 3. All linear dimensions are in millimeters (max/min). 4. Coplanarity: Max. 0.1mm 40 L AMIC Technology Corp. unit: mm ...
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... E 7.70 7.90 E 5.18 5. 1.27 BSC L 0.50 0.65 θ 0° - Notes: Maximum allowable mold flash is 0.15mm at the package ends and 0.25mm between leads 41 C θ L Max 2.16 0.25 1.91 0.48 0.25 5.33 8.10 5.38 0.80 8° AMIC Technology Corp. unit: mm ...
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... A25L020/A25L010/A25L512 Series θ Dimensions in mm Min Nom Max - - 1.200 0.050 - 0.150 0.800 1.000 1.050 0.190 - 0.300 0.090 - 0.200 6.200 6.400 6.600 4.300 4.400 4.500 - 0.650 - 2.900 3.000 3.100 0.450 0.600 0.750 - 1.000 - - - 0.100 - 0° 8° AMIC Technology Corp. unit: inches/mm ...
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... A25L020/A25L010/A25L512 Series unit: inches/ Bottom View Dimensions in mm Nom Max 0.55 0.60 0 0.035 0.05 - 0.40 0.425 - 0.152 - 0.25 0.30 2.00 2.10 1.60 1.70 3.00 3.10 0.20 0.30 - 0.50 - 0. AMIC Technology Corp. Pin1 I.D. ...