MAX149AEAP Maxim Integrated Products, MAX149AEAP Datasheet - Page 17
MAX149AEAP
Manufacturer Part Number
MAX149AEAP
Description
ADC (A/D Converters) Integrated Circuits (ICs)
Manufacturer
Maxim Integrated Products
Datasheet
1.MAX148BCAP.pdf
(23 pages)
Specifications of MAX149AEAP
Architecture
SAR
Conversion Rate
133 KSPs
Input Type
Voltage
Maximum Power Dissipation
640 mW
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
SSOP-20
Minimum Operating Temperature
- 40 C
Lead Free Status / Rohs Status
No
Software power-down is activated using bits PD1 and
PD0 of the control byte. As shown in Table 5, PD1 and
PD0 also specify the clock mode. When software shut-
down is asserted, the ADC operates in the last specified
clock mode until the conversion is complete. Then the
ADC powers down into a low quiescent-current state.
In internal clock mode, the interface remains active
and conversion results may be clocked out after the
MAX148/MAX149 enter a software power-down.
Figure 14b. MAX149 Supply Current vs. Conversion Rate,
FASTPD
Figure 14c. Typical Reference-Buffer Power-Up Delay vs.
Time in Shutdown
10,000
1000
100
2.0
1.5
1.0
0.5
0
1
0
0.001
TYPICAL REFERENCE-BUFFER POWER-UP
0.1
vs. CONVERSION RATE (USING FASTPD)
R
CODE = 1010101000
______________________________________________________________________________________
LOAD
DELAY vs. TIME IN SHUTDOWN
+2.7V to +5.25V, Low-Power, 8-Channel,
1
AVERAGE SUPPLY CURRENT
= ∞
0.01
CONVERSION RATE (Hz)
TIME IN SHUTDOWN (s)
10
8 CHANNELS
100
0.1
1k
Software Power-Down
10k
1 CHANNEL
1
100k
1M
10
The first logical 1 on DIN is interpreted as a start bit and
powers up the MAX148/MAX149. Following the start bit, the
data input word or control byte also determines clock mode
and power-down states. For example, if the DIN word con-
tains PD1 = 1, then the chip remains powered up. If PD0
= PD1 = 0, a power-down resumes after one conversion.
Pulling SHDN low places the converter in hardware pow-
er-down (Table 6). Unlike software power-down mode, the
conversion is not completed; it stops coincidentally with
SHDN being brought low. SHDN also controls the clock
frequency in internal clock mode. Leaving SHDN uncon-
nected sets the internal clock frequency to 1.8MHz. When
returning to normal operation with SHDN unconnected,
there is a t
is the capacitive loading on the SHDN pin. Pulling SHDN
high sets internal clock frequency to 225kHz. This feature
eases the settling-time requirement for the reference volt-
age. With an external reference, the MAX148/MAX149
can be considered fully powered up within 2Fs of actively
pulling SHDN high.
The MAX148/MAX149 auto power-down modes can
save considerable power when operating at less than
maximum sample rates. Figures 13, 14a, and 14b show
the average supply current as a function of the sampling
rate. The following discussion illustrates the various
power-down sequences.
The following examples show two different power-down
sequences. Other combinations of clock rates, compen-
sation modes, and power-down modes may give lowest
power consumption in other applications.
Figure 14a depicts the MAX149 power consumption for
one or eight channel conversions utilizing full power-
down mode and internal-reference compensation. A
0.01FF bypass capacitor at REFADJ forms an RC filter
with the internal 20kI reference resistor with a 0.2ms
time constant. To achieve full 10-bit accuracy, 8 time
constants or 1.6ms are required after power-up. Waiting
this 1.6ms in FASTPD mode instead of in full power-up
can reduce power consumption by a factor of 10 or
more. This is achieved by using the sequence shown in
Figure 15.
RC
Serial 10-Bit ADCs
delay of approximately 2MI x C
Power-Down Sequencing
Conversions/Channel/Second
Lowest Power at Up to 500
Hardware Power-Down
L
, where C
17
L