MAX5721EUA-T Maxim Integrated Products, MAX5721EUA-T Datasheet - Page 9

• Manufacturer Part Number: MAX5721EUA-T
• Description: DAC (D/A Converters)
• Manufacturer: Maxim Integrated Products

Specifications of MAX5721EUA-T

• Number Of Converters: 2
• Resolution: 10 bit
• Interface Type: Serial (3-Wire, SPI, QSPI, Microwire)
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: UMAX
• Minimum Operating Temperature: - 40 C
• Lead Free Status / Rohs Status: No

The MAX5721 contains two 10-bit, voltage-output, low-
power digital-to-analog converters (DACs). Each DAC
employs a resistor string architecture that converts a
10-bit digital input word to an equivalent analog output
voltage proportional to the applied reference voltage.
The MAX5721 shares one reference input (REF)
between both DACs. The MAX5721 includes rail-to-rail
output buffer amplifiers for each DAC, and input logic
for simple microprocessor (µP), and CMOS interfaces.
The power-supply range is from +2.7V to +5.5V
(Functional Diagram). The MAX5721’s reference input
accepts a voltage range from 0 to V
mode the reference input is high impedance. The
MAX5721 is compatible with the 3-wire SPI, QSPI,
MICROWIRE, and DSP serial interface with Schmitt-trig-
gered logic inputs.
The reference input accepts positive DC and AC sig-
nals. The voltage at REF sets the full-scale output volt-
age of both DACs. The reference input voltage range is
0 to V
at REF can vary from GND to V
(V
voltage source as:
where D is the decimal equivalent of binary DAC input
code ranging from 0 to 1023. V
All DACs are internally buffered at the output. The buffer
amplifiers have both rail-to-rail common mode and (GND
to V
stable with C
are disabled during power-up and individual DAC out-
puts are shorted to GND through a 100k resistor. Buffer
amplifiers can individually or altogether be powered-
down by programming the input register control bits.
During power down, contents of the input and DAC reg-
isters remain the same. On wake-up all DAC outputs are
restored to their pre-power-down voltage values.
In power-down mode, the DAC outputs are pro-
grammed to one of three output states, 1k , 100k , or
floating (Table 1). The REF input is high impedance
(2M
reference; therefore, the system reference does not
have to be powered-down. The DAC outputs return to
the values contained in the registers when brought out
of power-down. The recovery time, from total power-
OUT_
REF
Reference Input and DAC Output Range
DD
typ) to conserve current drain from the system
) are represented by a digitally programmable
) output voltage range. The buffers are unity-gain
. The impedance at REF is 90k . The voltage
L
= 200pF and R
V
OUT_
_______________________________________________________________________________________
10-Bit, Low-Power, Dual, Voltage-Output
Detailed Description
= (V
Output Buffer Amplifiers
REF
L
REF
✕
DD
Power-Down Mode
= 5k . Buffer amplifiers
D) / 2
. The output voltages
is the voltage at REF.
DD
10
. In power-down
DAC with Serial Interface
down to power-up, is 8µs. This extra time is needed to
allow the internal bias to wake-up. Power-down mode
reduces current consumption to 0.5µA.
The MAX5721 digital interface is a standard 3-wire con-
nection compatible with SPI/QSPI/MICROWIRE/DSP
interfaces. The chip-select input (CS) frames the serial
data loading at DIN. Immediately following CS high-to-
low transition, the data is shifted synchronously and
latched into the input register on the falling edge of the
serial clock input (SCLK). After 16 bits have been
loaded into the serial input register, it transfers its con-
tents to the DAC latch. CS may then either be held low
or brought high. CS must be brought high for a mini-
mum of 80ns before the next write sequence, since a
write sequence is initiated on a falling edge of CS. Not
keeping CS low during the first 15 SCLK cycles dis-
cards input data. The serial clock (SCLK) can idle
either high or low between transitions.
The MAX5721 has two internal registers per DAC, the
input register and the DAC register. The input register
holds the data that is waiting to be shifted to the DAC reg-
ister. Both input registers can be loaded without updating
the output. This function is useul when both outputs need
to be updated at the same time. The input register can be
made transparent. When the input register is transparent,
the data written into DIN loads directly to the DAC register
and the output is updated. The DAC output is not updat-
ed until data is written to the DAC register. See Table 2 for
a list of serial-interface programming commands.
The MAX5721 has an internal POR circuit. At power-up
all DACs are powered-down and OUT_ is terminated to
GND through 100k
DAC registers are cleared to all zero. An 8µs recovery
time after issuing a wake-up command is needed
before writing to the DAC registers. Power-down mode
control commands can be applied immediately with no
recovery time.
C3-C0 are control bits. The data bits D9 to D0 are in
straight binary format. Set bits S1 and S0 to zero. All
zeros correspond to zero scale and all ones corre-
spond to full scale.
The digital inputs are compatible with CMOS logic. In
order to save power and reduce input to output cou-
pling, SCLK and DIN input buffers are powered down
immediately after completion of shifting 16 bits into the
input shift register. A high to low transition at CS powers
up SCLK and DIN input buffers.
resistors. Contents of input and
3-Wire Serial Interface
Power-On Reset (POR)
Digital Inputs
9