MC100LVEL51DT ON Semiconductor, MC100LVEL51DT Datasheet

Flip Flops 3.3V/5V ECL D-Type

MC100LVEL51DT

Manufacturer Part Number
MC100LVEL51DT
Description
Flip Flops 3.3V/5V ECL D-Type
Manufacturer
ON Semiconductor
Datasheet

Specifications of MC100LVEL51DT

Number Of Circuits
1
Logic Family
100
Logic Type
D-Type Flip-Flop
Polarity
Inverting/Non-Inverting
Input Type
Single-Ended
Propagation Delay Time
0.52 ns
Supply Voltage (max)
- 3.8 V, 3.8 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
TSSOP-8
Minimum Operating Temperature
- 40 C
Supply Voltage (min)
- 3 V or 3 V
Lead Free Status / Rohs Status
No RoHS Version Available

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC100LVEL51DTG
Manufacturer:
ON Semiconductor
Quantity:
135
MC100LVEL51
3.3V ECL Differential Clock
D Flip‐Flop
Description
device is functionally equivalent to the EL51 device, but operates from a
3.3 V supply. With propagation delays and output transition times
essentially equal to the EL51, the LVEL51 is ideally suited for those
applications which require the ultimate in AC performance at 3.3 V V
the master portion of the flip-flop when the clock is LOW and is
transferred to the slave, and thus the outputs, upon a positive transition of
the clock. The differential clock inputs of the LVEL51 allow the device to
be used as a negative edge triggered flip-flop.
under open input conditions. When left open, the CLK input will be
pulled down to V
Features
© Semiconductor Components Industries, LLC, 2008
August, 2008 − Rev. 6
The MC100LVEL51 is a differential clock D flip-flop with reset. The
The reset input is an asynchronous, level triggered signal. Data enters
The differential input employs clamp circuitry to maintain stability
>200 V Machine Model
with V
with V
For Additional Information, see Application Note AND8003/D
Oxygen Index: 28 to 34
475 ps Propagation Delay
2.8 GHz Toggle Frequency
ESD Protection: >4 kV Human Body Model,
The 100 Series Contains Temperature Compensation
PECL Mode Operating Range: V
NECL Mode Operating Range: V
Internal Input Pulldown Resistors
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Moisture Sensitivity Level 1
Flammability Rating: UL 94 V−0 @ 0.125 in,
Transistor Count = 114 devices
Pb−Free Packages are Available
EE
EE
= −3.0 V to −3.8 V
= 0 V
EE
and the CLK input will be biased at V
CC
CC
= 3.0 V to 3.8 V
= 0 V
CC
/2.
1
CC
.
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
CASE 506AA
CASE 948R
MN SUFFIX
*For additional marking information, refer to
DT SUFFIX
CASE 751
D SUFFIX
TSSOP−8
8
(Note: Microdot may be in either location)
Application Note AND8002/D.
SOIC−8
8
DFN8
ORDERING INFORMATION
1
1
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
M = Date Code
G = Pb−Free Package
http://onsemi.com
Publication Order Number:
DIAGRAMS*
8
1
MARKING
MC100LVEL51/D
8
1
ALYWG
1
KVL51
ALYW
KV51
G
G
4

Related parts for MC100LVEL51DT

MC100LVEL51DT Summary of contents

Page 1

MC100LVEL51 3.3V ECL Differential Clock D Flip‐Flop Description The MC100LVEL51 is a differential clock D flip-flop with reset. The device is functionally equivalent to the EL51 device, but operates from a 3.3 V supply. With propagation delays and output transition times ...

Page 2

R D CLK CLK Figure 1. Logic Diagram and Pinout Assignment Table 1. PIN DESCRIPTION PIN FUNCTION CLK, CLK ECL Differential Clock Input Q, Q ECL Differential Output D ECL D Input R ECL Reset Input V Positive Supp;y CC ...

Page 3

Table 3. MAXIMUM RATINGS Symbol Parameter V PECL Mode Power Supply CC V NECL Mode Power Supply EE V PECL Mode Input Voltage I NECL Mode Input Voltage I Output Current out T Operating Temperature Range A T Storage Temperature ...

Page 4

Table 4. LVPECL DC CHARACTERISTICS Symbol Characteristic I Power Supply Current EE V Output HIGH Voltage (Note Output LOW Voltage (Note Input HIGH Voltage (Single−Ended Input LOW Voltage (Single−Ended Input ...

Page 5

Table 6. AC CHARACTERISTICS V CC Symbol Characteristic f Maximum Toggle Frequency max t Propagation Delay PLH t to Output PHL t Setup Time S t Hold Time H t Reset Recovery RR t Minimum Pulse PW Width t Cycle−to−Cycle ...

Page 6

... ORDERING INFORMATION Device MC100LVEL51D MC100LVEL51DG MC100LVEL51DR2 MC100LVEL51DR2G MC100LVEL51DT MC100LVEL51DTG MC100LVEL51DTR2 MC100LVEL51DTR2G MC100LVEL51MNR4 MC100LVEL51MNR4G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D AN1406/D AN1503/D ...

Page 7

... G C SEATING PLANE −Z− 0.25 (0.010 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE 0.10 (0.004 SOLDERING FOOTPRINT* 1 ...

Page 8

K 8x REF 0.10 (0.004) 0.15 (0.006 L −U− PIN 1 IDENT 0.15 (0.006 −V− C 0.10 (0.004) D −T− G SEATING PLANE PACKAGE DIMENSIONS TSSOP−8 ...

Page 9

... Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303− ...

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