MC100EPT24D ON Semiconductor, MC100EPT24D Datasheet

Translation - Voltage Levels 3.3V LVTTL/LVCMOS

MC100EPT24D

Manufacturer Part Number
MC100EPT24D
Description
Translation - Voltage Levels 3.3V LVTTL/LVCMOS
Manufacturer
ON Semiconductor
Datasheet

Specifications of MC100EPT24D

Logic Type
Translator
Logic Family
ECL
Package / Case
SOIC-8
Translation
LVCMOS/LVTTL to LVECL
Propagation Delay Time
0.8 ns
Supply Voltage (max)
- 3.6 V
Supply Voltage (min)
- 3 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Dc
03+
Lead Free Status / Rohs Status
No RoHS Version Available

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MC100EPT24
3.3V LVTTL/LVCMOS to
Differential LVECL Translator
Description
translator. Because LVECL levels and LVTTL/LVCMOS levels are
used, a −3.3 V, +3.3 V and ground are required. The small outline
8−lead package and the single gate of the EPT24 makes it ideal for
those applications where space, performance, and low power are at a
premium.
Features
© Semiconductor Components Industries, LLC, 2008
August, 2008 − Rev. 9
The MC100EPT24 is a LVTTL/LVCMOS to differential LVECL
V
350 ps Typical Propagation Delay
Maximum Input Clock Frequency > 1.0 GHz Typical
The 100 Series Contains Temperature Compensation
Operating Range: V
PNP LVTTL Input for Minimal Loading
Q Output will Default HIGH with Input Open
Pb−Free Packages are Available
EE
= −3.6 V to −3.0 V; GND = 0 V
CC
= 3.0 V to 3.6 V;
1
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
*For additional marking information, refer to
8
(Note: Microdot may be in either location)
Application Note AND8002/D.
8
ORDERING INFORMATION
1
1
A
L
Y
W
M
G
http://onsemi.com
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Date Code
= Pb−Free Package
CASE 506AA
CASE 751
D SUFFIX
MN SUFFIX
CASE 948R
SOIC−8
DT SUFFIX
TSSOP−8
MARKING DIAGRAMS*
DFN8
Publication Order Number:
MC100EPT24/D
8
1
8
1
KPT24
ALYW
ALYWG
1
KA24
G
G
4

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MC100EPT24D Summary of contents

Page 1

MC100EPT24 3.3V LVTTL/LVCMOS to Differential LVECL Translator Description The MC100EPT24 is a LVTTL/LVCMOS to differential LVECL translator. Because LVECL levels and LVTTL/LVCMOS levels are used, a −3.3 V, +3.3 V and ground are required. The small outline 8−lead package and the ...

Page 2

LVTTL D 2 LVECL Figure 1. 8−Lead Pinout (Top View) and Logic Diagram Table 2. ATTRIBUTES Characteristics Internal Input Pulldown Resistor Internal Input Pullup Resistor ESD Protection Moisture Sensitivity, Indefinite Time Out of ...

Page 3

Table 3. MAXIMUM RATINGS Symbol Parameter V Positive Power Supply CC V Negative Power Supply EE V Input Voltage IN I Output Current out T Operating Temperature Range A T Storage Temperature Range stg Thermal Resistance (Junction−to−Ambient ...

Page 4

Table 6. AC CHARACTERISTICS V Symbol Characteristic f Maximum Input Clock Frequency (Fig- max ure Propagation Delay to PLH t Output Differential (Note 6) PHL t RMS Random Clock Jitter (Figure 2) JITTER t Output Rise/Fall Times ...

Page 5

... ORDERING INFORMATION Device MC100EPT24D MC100EPT24DG MC100EPT24DR2 MC100EPT24DR2G MC100EPT24DT MC100EPT24DTG MC100EPT24DTR2 MC100EPT24DTR2G MC100EPT24MNR4 MC100EPT24MNR4G †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Resource Reference of Application Notes AN1405/D AN1406/D ...

Page 6

... G C SEATING PLANE −Z− 0.25 (0.010 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. PACKAGE DIMENSIONS SOIC−8 NB CASE 751−07 ISSUE 0.10 (0.004 SOLDERING FOOTPRINT* 1 ...

Page 7

K 8x REF 0.10 (0.004) 0.15 (0.006 L −U− PIN 1 IDENT 0.15 (0.006 −V− C 0.10 (0.004) D −T− G SEATING PLANE PACKAGE DIMENSIONS TSSOP−8 ...

Page 8

... Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303− ...

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