74HCT646D NXP Semiconductors, 74HCT646D Datasheet - Page 2

• Manufacturer Part Number: 74HCT646D
• Description: Bus Transceivers OCTAL TRANSCEIVER/ REGISTER 3-S
• Manufacturer: NXP Semiconductors

Specifications of 74HCT646D

• Logic Type: CMOS
• Logic Family: HCT
• Number Of Channels Per Chip: 8
• Input Level: TTL
• Output Level: CMOS
• Output Type: 3-State
• High Level Output Current: - 6 mA
• Low Level Output Current: 6 mA
• Propagation Delay Time: 44 ns
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Maximum Operating Temperature: + 125 C
• Package / Case: SO-24
• Function: Bus Transceiver / Register
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Number Of Circuits: 1
• Polarity: Non-Inverting
• Lead Free Status / Rohs Status: Details
• Other names: 74HCT646D,652

Philips Semiconductors
FEATURES
GENERAL DESCRIPTION
The 74HC/HCT646 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT646 consist of bus transceiver circuits with
3-state outputs, D-type flip-flops, and control circuitry
arranged for multiplexed transmission of data directly from
the internal registers. Data on the “A” or “B” bus will be
QUICK REFERENCE DATA
GND = 0 V; T
Notes
1. C
2. For HC the condition is V
ORDERING INFORMATION
See
September 1993
SYMBOL
t
f
C
C
PHL
max
Independent register for A and B buses
Multiplexed real-time and stored data
Output capability: bus driver
I
Octal bus transceiver/register; 3-state
I
PD
CC
f
f
C
V
For HCT the condition is V
i
o
“74HC/HCT/HCU/HCMOS Logic Package Information”
/ t
CC
PD
L
category: MSI
= output frequency in MHz
= input frequency in MHz
(C
PLH
= output load capacitance in pF
P
is used to determine the dynamic power dissipation (P
= supply voltage in V
L
D
= C
V
amb
CC
PARAMETER
propagation delay
maximum clock frequency
input capacitance
power dissipation capacitance per channel
PD
2
= 25 C; t
V
f
o
CC
) = sum of outputs
2
f
r
i
= t
+
I
I
f
= GND to V
= GND to V
= 6 ns
(C
L
A
n
, B
V
CC
n
to B
2
CC
CC
n
f
o
, A
) where:
1.5 V
n
2
.
CONDITIONS
C
notes 1 and 2
clocked into the registers as the appropriate clock
(CP
enable (OE) and direction (DIR) inputs are provided to
control the transceiver function. In the transceiver mode,
data present at the high-impedance port may be stored in
either the “A” or “B” register, or in both. The select source
inputs (S
(transparent mode) data. The direction (DIR) input
determines which bus will receive data when OE is active
(LOW). In the isolation mode (OE = HIGH), “A” data may
be stored in the “B” register and/or “B” data may be stored
in the “A” register.
When an output function is disabled, the input function is
still enabled and may be used to store and transmit data.
Only one of the two buses, A or B, may be driven at a time.
The “646” is functionally identical to the “648”, but has
non-inverting data paths.
L
= 15 pF; V
D
in W):
AB
and CP
AB
and S
CC
BA
= 5 V
) goes to a HIGH logic level. Output
BA
) can multiplex stored and real-time
11
69
3.5
30
HC
TYPICAL
74HC/HCT646
Product specification
13
85
3.5
33
HCT
ns
MHz
pF
pF
UNIT