MAX9206EAI Maxim Integrated Products, MAX9206EAI Datasheet
MAX9206EAI
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MAX9206EAI Summary of contents
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... Parallel LVCMOS/LVTTL Output 600Mbps Throughput (MAX9208) o Programmable Output Strobe Edge o Pin Compatible to DS92LV1212A and DS92LV1224 PART Applications MAX9206EAI+ MAX9206EAI/V+ -40°C to +85°C 28 SSOP MAX9208EAI+ + Denotes a lead(Pb)-free/RoHS-compliant package. /V denotes an automotive qualified part. Pin Configuration appears at end of data sheet. BUS LVDS OUT+ RI+ 100Ω ...
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Bus LVDS Deserializers ABSOLUTE MAXIMUM RATINGS AVCC, DVCC to AGND, DGND................................-0.3V to +4V RI+, RI- to AGND, DGND .........................................-0.3V to +4V All Other Pins to DGND ..............................-0. ROUT_ Short-Circuit Duration (Note 1) ......................Continuous Continuous Power Dissipation (T ...
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AC ELECTRICAL CHARACTERISTICS ( +3.0V to +3.6V, C AVCC DVCC 2. -40°C to +85°C, unless otherwise noted. Typical values are 0.2V ...
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Bus LVDS Deserializers AC ELECTRICAL CHARACTERISTICS (continued +3.0V to +3.6V AVCC DVCC | | to 2. -40°C to +85°C, unless otherwise noted. Typical values are at V ...
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PIN NAME 1, 12, 13 AGND Analog Ground Recovered Clock Strobe Edge Select. LVTTL/LVCMOS level input. Drive RCLK_ R/F high to strobe 2 RCLK_R/F ROUT_ on the rising edge of RCLK. Drive RCLK_R/F low to strobe ROUT_ on the falling ...
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Bus LVDS Deserializers IN2 V - 0.3V CC RI+ R IN1 R IN1 RI- Figure 2. Input Fail-Safe Circuit START SYMBOL N BIT RCLK ROUT_ Figure 4. Input-to-Output Delay RCLK RCLK_R/F = ...
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PWRDN REFCLK t RFCP RI t ZHLK LOCK HIGH-Z RCLK HIGH-Z ROUT_ HIGH-Z 2048 x t Figure 7. PLL Lock Time from PWRDN REFCLK t RFCP RI LOCK RCLK ROUT_ Figure 8. Deserializer PLL Lock Time from _______________________________________________________________________________________ 10-Bit Bus ...
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Bus LVDS Deserializers Detailed Description The MAX9206/MAX9208 deserialize a BLVDS serializ- er's output into 10-bit wide parallel LVCMOS/LVTTL data and a parallel rate clock. The MAX9206/MAX9208 include a PLL that locks to the frequency and phase of the serial ...
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Table 1. Typical Lock Times REFCLK 16MHz FREQUENCY DATA PSEUDORANDOM PATTERN DATA Maximum 0.749μs Maximum (Clock 11.99 Cycles) Average 0.318μs Average (Clock 5.09 Cycles) Minimum 0.13μs Minimum (Clock 2.08 Cycles) Note: Pseudorandom lock performed with PRBS pattern, ...
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Bus LVDS Deserializers t /12 RCP Figure 9. Input Jitter Tolerance Applications Information Power-Supply Bypassing Bypass each supply pin with high-frequency surface- mount ceramic 0.1µF and 0.001µF capacitors in paral- lel as close to the ...
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Table 2. Input/Output Function Table LOGIC INPUTS CONDITIONS PWRDN REN X Low Power applied and stable Low High Deserializer initialized High High Deserializer initialized X = Don’t care. The MAX9206/MAX9208 deserializers can operate in a variety of topologies. Examples of ...
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... Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 12 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2010 Maxim Integrated Products DESCRIPTION Maxim is a registered trademark of Maxim Integrated Products, Inc ...