74LVC10APW NXP Semiconductors, 74LVC10APW Datasheet - Page 8

Gates (AND / NAND / OR / NOR) TRIPLE 3-INPUT NAND GATE

74LVC10APW

Manufacturer Part Number
74LVC10APW
Description
Gates (AND / NAND / OR / NOR) TRIPLE 3-INPUT NAND GATE
Manufacturer
NXP Semiconductors
Datasheet

Specifications of 74LVC10APW

Product
NAND
Logic Family
LVC
Number Of Gates
3
Number Of Lines (input / Output)
3 / 1
High Level Output Current
- 24 mA
Low Level Output Current
24 mA
Propagation Delay Time
3.9 ns
Supply Voltage (max)
3.6 V
Supply Voltage (min)
1.2 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
TSSOP-14
Minimum Operating Temperature
- 40 C
Lead Free Status / Rohs Status
 Details
Other names
74LVC10APW,112

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
74LVC10APW
Manufacturer:
NXP/恩智浦
Quantity:
20 000
Philips Semiconductors
AC WAVEFORMS
2003 Jun 20
handbook, full pagewidth
Triple 3-input NAND gate
V
V
V
Definitions for test circuit:
R
C
R
t
M
M
OL
L
L
T
PLH
= load resistor.
= load capacitance including jig and probe capacitance.
= termination resistance should be equal to the output impedance Z
= 1.5 V at V
= 0.5V
and V
/t
TEST
PHL
CC
SWITCH POSITION
OH
at V
are the typical output voltage drop that occur with the output load.
CC
CC
< 2.7 V.
2.7 V.
open
Fig.6 Input (nA, nB and nC) to output (nY) propagation delays.
S1
GENERATOR
handbook, halfpage
PULSE
nA, nB, nC input
nY output
Fig.7 Load circuitry for switching times.
<2.7 V
2.7 to 3.6 V
GND
V OH
V OL
V I
V I
V
CC
R T
D.U.T.
V CC
V M
o
of the pulse generator.
V M
V
2.7 V
8
CC
V O
t PHL
V
I
C L =
50 pF
R L = 500
R L = 500
S1
MNA760
MNA815
t PLH
2
open
GND
V CC
Product specification
74LVC10A

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