WGCE5037 S L9FV Intel, WGCE5037 S L9FV Datasheet - Page 16

• Manufacturer Part Number: WGCE5037 S L9FV
• Manufacturer: Intel

Specifications of WGCE5037 S L9FV

• Lead Free Status / Rohs Status: Compliant

3.1
Figure 4 shows a typical application using a CE6313 as a demodulator. This is available as a reference design
(CE9542) from Intel Corporation.
The design uses a standard two layer board. All components are mounted on the upper surface with the lower
surface as a ground plane. The RF input requires a coupling capacitor and series inductor for optimum matching.
The RF bypass output requires a coupling capacitor. Good decoupling should be used - these components should
be mounted as close to the device as practicable.
All ground contact to the CE5037 is to the ground ‘paddle’ on the underside of the package. This must be soldered
fully to the board to achieve best thermal and electrical contact. It is recommended that an array of vias (4 x 4) is
used to achieve good contact to the ground plane underneath the device
A common crystal reference can be used for the tuner and demodulator. The crystal oscillator capacitors are
optimised for a 10.111 MHz reference.
Sensitivity is optimised by minimizing interaction from digital signal activity in the demodulator. This is achieved by
filtering in the agc control, and filter networks in the baseband I and Q signals between the demodulator and
CE5037. These networks should be mounted as close to the CE5037 as possible.
The typical performance from the reference design is shown in the table below:
Further information is provided in CE9542 user guides.
The CE5037 can also be used with other demodulators. If the demodulator has a single-ended input then the
CE5037 can be used with a single-ended outputs ie IOUT and QOUT. The unused outputs should be loaded with
an equivalent load to the demodulator input to maintain a good balanced configuration. The optimum output level
for the demodulator can be achieved by adjusting the post filter baseband gain.
3.2
The excellent performance of the CE5037 makes the device also suitable for the higher level modulation schemes
(8PSK) used for DVB-S2. In the critical areas of quadrature accuracy and phase noise, typical performance is
shown in the following table.
Sensitivity
C/N 27.5MS/s rate 7/8
2e-4 post Viterbi BER
C/N 2MS/s rate 7/8
2e-4 post Viterbi BER
Interference Rejection Ratio
27.5 MS/s rate 7/8.
Interferers at -25 dBm
General Design Guidelines
DVB-S2 Applications
Parameter
Table 23 - Typical Performance using CE5037 and CE6313
Typ.
-83
8.3
8.1
8.1
8.2
8.0
8.0
32
35
45
35
Units
dBm
Intel Corporation
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
CE5037
16
QEF 27.5MS/s rate 7/8
No added noise
Input = -69 dBm
Input = -81dBm
N+1
N+4
N+10
2 Interferers at -25dBm
-45 dBm
-23 dBm
-45 dBm
-23 dBm
Notes
Data Sheet