U3741BM-P2FLG3 19 Atmel, U3741BM-P2FLG3 19 Datasheet - Page 18
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U3741BM-P2FLG3 19
Manufacturer Part Number
U3741BM-P2FLG3 19
Description
Manufacturer
Atmel
Datasheet
1.U3741BM-P2FLG3_19.pdf
(32 pages)
Specifications of U3741BM-P2FLG3 19
Operating Frequency (max)
450000kHz
Operating Temperature (min)
-40C
Operating Temperature (max)
105C
Operating Temperature Classification
Industrial
Operating Supply Voltage (min)
4.5V
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Lead Free Status / Rohs Status
Not Compliant
Table 3. Effect of the Configuration Words within the Registers
Table 4. Effect of the Configuration Word BR_Range
OFF Command
OPMODE Register
LIMIT Register
18
Bit1 Bit2
(Default)
(Default)
1
0
0
0
0
Baud1
1
1
0
0
0
0
1
1
U3741BM
Lim_min5 Lim_min4 Lim_min3 Lim_min2 Lim_min1 Lim_min0 Lim_max5 Lim_max4 Lim_max3 Lim_max2 Lim_max1 Lim_max0
Baud1
Bit2
BR_Range
0
0
BR_Range
Baud0
Bit4
0
0
Baud0
0
1
0
1
BitChk1
Bit5
1
1
Lim_min
Table 2. Effect of Bit 1 and Bit 2 in Programming the Registers
Table 4 and the following illustrate the effect of the individual configuration words. The
default configuration is highlighted for each word.
BR_Range sets the appropriate baud rate range. At the same time it defines XLim. XLim
is used to define the bit check limits T
POUT can be used to control the sensitivity of the receiver. In that application, POUT is
set to 1 to reduce the sensitivity. This implies that the receiver operates with full sensitiv-
ity after a POR.
N
Bitcheck
BitChk0
Bit 1
Baud Rate Range/Extension Factor for Bit Check Limits (XLim)
BR_Range0 (application USA/Europe: BR_Range0 = 1.0 kBaud to 1.8 kBaud) (Default)
XLim = 8 (Default)
BR_Range1 (application USA/Europe: BR_Range1 = 1.8 kBaud to 3.2 kBaud)
XLim = 4
BR_Range2 (application USA/Europe: BR_Range2 = 3.2 kBaud to 5.6 kBaud)
XLim = 2
BR_Range3 (Application USA/Europe: BR_Range3 = 5.6 kBaud to 10 kBaud)
XLim = 1
Bit6
1
0
0
0
1
POUT
V
Bit7
POUT
0
1
Bit 2
x
1
0
Sleep4
Bit8
0
0
Action
The receiver is set back to polling mode (OFF command)
The OPMODE register is programmed
The LIMIT register is programmed
Sleep3
Bit9
1
0
Lim_min
Sleep2
Bit10
Sleep
0
1
and T
Lim_max
Sleep1
Bit11
1
1
Lim_max
as shown in Table 4.
Sleep0
Bit12
1
0
X
Bit13
Sleep Std
0
0
4662B–RKE–10/04
X
Sleep
X
Sleep Temp
Bit14
0
0