MC13190FC Freescale Semiconductor, MC13190FC Datasheet - Page 8

• Manufacturer Part Number: MC13190FC
• Manufacturer: Freescale Semiconductor

Specifications of MC13190FC

• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

Application Information
The PLL is enabled, a delay of 10 µs is observed for the VCO and the PLL to settle, and then trimming is
begun. Trimming continues until TRIM_EN is taken low and should continue for a minimum of 100 µs.
After the TRIM_EN is taken low, the trim information is stored internally, a process that takes about 10 µs.
PLL_EN must remain high while the trim information is stored.
The frequency synthesizer uses a fixed 256 divider and must be enabled in both TRIM and TX mode. The
frequency synthesizer is not required in the receive mode and may be disabled. The frequency synthesizer
requires an external reference signal (IC Contact 8), FREF, and an external loop filter connected to IC
Contact 13.
3.2.3 Receive Mode
In Receive mode, the 2.4 GHz signals from the antenna are amplified by the LNA, peak detected in the
demodulator and filtered and amplified to produce the RX_DATA output. The response time after the first
time RX_EN is pulled high is set by the charging time of the demodulator bypass capacitor and is about
700 µs. Once the capacitor is charged, internal circuitry maintains the charge for at least one second and
the response time is reduced to around 7 µs. An 8-bit preamble allows for receive circuitry setting. The
receiver baseband filter is optimized for Manchester encoded 5 Mbps data. The Receive sequence is shown
in Figure 5.
3.3 Transmit and Receive Sequencing
Figure 6 shows the sequencing and timing for a typical Trim, Transmit, Receive and Re-transmit cycle.
Note that the PLL and VCO (PLL_EN) are off during the Receive cycle. This sequence can be repeated as
often as needed and is controlled by the applications software. The TRIM cycle should be repeated at
regular intervals of 1 to 10 seconds or when the temperature and/or voltage have changed.
8
Figure 5. Recommended Timing During Receive Mode
Figure 4. Recommended Timing During Trim Mode
RX_DATA
TRIM_EN
RX_EN
PLL_EN
10 µ s
MC13190 Advance Information
* 700 µ s for 1
7.0 µs thereafter, assuming TX Cycle
*
8-Bit Preamble
No Specific Time Limit
5Mbps Receive Data
at least 100 µ s
st
RX_EN
≤
10 µ s
1 sec
MOTOROLA