WJCE6353 Intel, WJCE6353 Datasheet - Page 13

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WJCE6353

Manufacturer Part Number
WJCE6353
Description
COFDM Terrestrial Demodulator 64-Pin LQFP
Manufacturer
Intel
Datasheet

Specifications of WJCE6353

Pin Count
64
Screening Level
Commercial
Package Type
LQFP
Package
64LQFP
Operating Temperature
-10 to 80 °C
Lead Free Status / Rohs Status
Compliant

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2.4
Adjacent channels, in particular the Nicam digital sound signal associated with analogue channels, are filtered prior to the
FFT.
2.5
CE6353 uses digital timing recovery and this eliminates the need for an external VCXO. The ADC samples the signal at a
fixed rate, for example, 45.056 MHz. Conversion of the 45.056 MHz signal to the OFDM sample rate is achieved using the
time-varying interpolator. The OFDM sample rate is 64/7 MHz for 8 MHz and this is scaled by factors 6/8 and 7/8 for 6
and 7 MHz channel bandwidths. The nominal ratio of the ADC to OFDM sample rate is programmed in a CE6353 register
(defaults are for 45 MHz sampling and 8 MHz OFDM). The clock recovery phase locked loop in the CE6353 compensates
for inaccuracies in this ratio due to uncertainties of the frequency of the sampling clock.
2.6
There can be frequency offsets in the signal at the input to OFDM, partly due to tuner step size and partly due to
broadcast frequency shifts, typically 1/6 MHz. These are tracked out digitally, up to 1 MHz in 2 K and 8 K modes, without
the need for an analogue frequency control (AFC) loop.
The default frequency capture range has been set to ±286 kHz in the 2 K and 8 K mode. However, these values can be
increased, if necessary, by programming an on-chip register (see details in the design manual). It is recommended that a
larger capture range be used for channel scan in order to find channels with broadcast frequency shifts, without having to
adjust the tuner. After the OFDM module has locked (the AFC will have been previously disabled), the frequency offset
can be read from an on-chip register.
2.7
This module computes the optimum sample position to trigger the FFT in order to eliminate or minimize inter-symbol
interference in the presence of multi-path distortion. Furthermore, this trigger point is continuously updated to dynami-
cally adapt to time-variations in the transmission channel.
2.8
The FFT module uses the trigger information from the timing synchronization module to set the start point for an FFT. It
then uses either a 2 K or 8 K FFT to transform the data from the time domain to the frequency domain. An extremely
hardware-efficient and highly accurate algorithm has been used for this purpose.
2.9
This module subtracts the common phase offset from all the carriers of the OFDM signal to minimize the effect of the
tuner phase noise on system performance.
2.10
This consists of two parts. The first part involves estimating the channel frequency response from pilot information.
Efficient algorithms have been used to track time-varying channels with a minimum of hardware.
The second part involves applying a correction to the data carriers based on the estimated frequency response of the
channel. This module also generates dynamic channel state information (CSI) for every carrier in every symbol.
2.11
CE6353 contains several mechanisms to reduce the impact of impulse noise on system performance.
2.12
An OFDM frame consists of 68 symbols and a superframe is made up of four such frames. There is a set of TPS carriers in
every symbol and all these carry one bit of TPS. These bits, when combined, include information about the transmission
mode, guard ratio, constellation, hierarchy and code rate, as defined in ETS 300 744. In addition, the first eight bits of the
cell identifier are contained in even frames and the second eight bits of the cell identifier are in odd frames. The TPS
module extracts all the TPS data, and presents these to the host processor in a structured manner.
Adjacent Channel Filtering
Interpolation and Clock Synchronisation
Carrier Frequency Synchronisation
Symbol Timing Synchronisation
Fast Fourier Transform
Channel Equalisation
Impulse Filtering
Common Phase Error Correction
Transmission Parameter Signalling (TPS)
Intel Corporation
CE6353
Data Sheet
13

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