S19205CBI Applied Micro Circuits Corporation, S19205CBI Datasheet - Page 2

• Manufacturer Part Number: S19205CBI
• Manufacturer: Applied Micro Circuits Corporation

Specifications of S19205CBI

• Lead Free Status / Rohs Status: Not Compliant

KHATANGA
10 Gigabit Ethernet MAC and PHY/OC-192c POS Framer/Mapper
Overview and Applications
The S19205 is a dense VLSI device that integrates a 10GbE MAC, a
64B/66B Physical Coding Sublayer (PCS) and a WAN Interface Sub-
layer (WIS) as baselined by the IEEE P802.3ae task force. Optionally,
it can be configured to perform full-duplex mapping of packets into
SONET/SDH payloads at OC-192c rate (POS). When configured for
SONET/SDH operation, the S19205 supports Automatic Protection
Switching (APS) as required in carrier-class equipment.
SONET/SDH Processing (WIS)
The S19205 implements SONET/SDH processing functions for a sin-
gle STS-192/STM-64 data stream. The S19205 performs full section,
line, and path overhead processing of all defined TOH/POH bytes,
including framing, scrambling/descrambling, alarm signal (AIS) inser-
tion/detection, remote failure insertion/detection (REI/RDI), section/
path trace insertion/capture (J0/J1) and bit interleaved parity (B1/B2/
B3) processing. The S19205 provides programmable Signal Fail (SF)
and Signal Degrade (SD) thresholds for B2 and B3 monitoring.
The S19205 is SONET and SDH standards compliant with Telcordia
GR-253, GR-499 and GR-1377, and ANSI T1. 105-1995, and ITU
G.707 and G.783.
POS HDLC Processing
The S19205 can be configured for HDLC processing for STS-192c/
AU-4-64c POS applications. When configured for POS HDLC pro-
cessing, the S19205’s transmit HDLC processor will provide the inser-
tion of HDLC framed packets into the STS SPE. It will perform packet
framing, provide interframe fill and TX FIFO error recovery. In addition,
it optionally performs payload scrambling (x
ency processing as required by RFC 2615 and will optionally generate
a 32 bit CRC.
The receive HDLC processor provides for the extraction of HDLC
frames, transparency removal, de-scrambling (if enabled), FCS error
checking and optionally deletes the HDLC address and control fields.
The S19205 also provides a robust set of counters and status/control
registers for performance monitoring via the microprocessor.
It is SONET/SDH standards compliant IETF RFC 1662 and RFC 2615.
10 Gigabit Ethernet MAC Processing
The 10GbE Medium Access Control block supports full-duplex traffic
at 10Gbps rates. In the transmit direction, it performs encapsulation of
packets received through the system interface into Ethernet frames. It
provides pad insertion to insure a minimum frame length, as well as
CRC generation. The MAC processing block also provides for pream-
ble, SFD and IFG generation.
In the receive direction, the MAC processing consists of Ethernet
framing and CRC validation, as well as monitoring of the size of the
received frame.
The MAC block also integrates an extensive set of counters for net-
work statistics collection in support of RMON and IETF standard MIBs.
2
43
+ 1), performs transpar-
Empowering Intelligent Optical Networks
The MAC supports flow control for both serial LAN (10Gbps) or WAN
(9.95Gbps) applications through the 802.3x MAC ‘PAUSE’ function-
ality.
64B/66B Encoder / Decoder
When configured for Ethernet operation, the PCS sublayer performs
frame scrambling and bit ordering before passing data to the WAN
Interface Sublayer or to the XSBI interface. 64B/66B block coding is
used to guarantee run length, transition density and DC balance of the
serial data stream. Data frames are delineated using “01” sync header.
Control frames are identified with a “10” sync header.
Line-side Interface
In 10GbE WAN PHY and OC-192c POS mode, the line-side interface
supports a 16-bit parallel bus operating at 622.08 MHz, compliant with
the OIF SFI-4 and the proposed IEEE P802.3ae XSBI interfaces. In
10GbE LAN PHY mode, the line side interface operates as a XSBI-
compliant 16-bit LVDS parallel interface operating at 644.53MHz.
System Interface
A 64-bit, 200MHz FlexBus-4
ets on the system side. FlexBus-4
Phase 1 Specification.
Microprocessor Interface
The user of the S19205 can select between an 8-bit asynchronous or
a 16-bit synchronous microprocessor interface for device control and
monitoring. The interface supports both Intel and Motorola type micro-
processors, and is capable of operating in either an interrupt driven or
polled-mode configurations.
Applications
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Core switches/routers
Multi-service switches
MAN switches
Direct Mapping of any traffic type in SONET/SDH STS-
192c/AU-4-64c payloads
Part Number S19205, Revision 1.6, February 2009
TM
interface is used for transferring pack-
TM
is compliant to the OIF SPI-4
Product Brief