S1201QFI Applied Micro Circuits Corporation, S1201QFI Datasheet

S1201QFI

Manufacturer Part Number

S1201QFI

Description

Manufacturer

Applied Micro Circuits Corporation

Datasheet

1.S1201QFI.pdf (2 pages)

Specifications of S1201QFI

Package Type

PQFP

Lead Free Status / Rohs Status

Not Compliant

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• Processes SONET/SDH STS-12c/(STM-4/AU-4-4c) or

• Terminates & generates SONET/SDH section, line, & path

• Provides an 8-bit parallel line-side interface operating at

• Generic 8-bit microprocessor interface for configuration,

• Scrambling/descrambling (1+X

• Selectable self-synchronous scrambler implementing (X

• Supports multiple devices sharing the same Utopia inter-

• Provides an 8-bit General Purpose I/O (GPIO) register and

• Provides an IEEE 1149.1 JTAG (Boundary Scan) test port.

• Provides internal loopback paths for diagnostics.

• Implemented in 0.35um/3.3V CMOS process technology

• Packaged in 208 pin PQFP.

CONGO

STS-12c/STS-3c POS/ATM SONET MAPPER

Features

STS-3c/STM-1 data streams with full duplex mapping of

ATM cells or packets (PPP or LAPS) into SONET/SDH

payloads.

layers, with transport/section E1, E2, F1 and DCC over-

head interfaces in both transmit and receive directions.

19.44/77.76 MHz, and a 16-bit Utopia Level 2 or

POS-PHY

25/50 MHz.

control, and status monitoring.

frame.

+1) polynomial for ATM and HDLC.

face when used in a multi-PHY configuration.

associated hardware interface pins.

S1201 Block Diagram

TX_FRAME_OUT

RX_SONET_CLK

TX_SONET_CLK

RX_FRAME_IN

RX_DATA[7:0]

TX_DATA[7:0]

RX_LOS

Level 2 compatible system-side interface at

FRAMER

) of SONET/SDH

TOH EXTRACT

MONITOR

TOH

TOH INSERT

SPE/VC & POH

GENERATE

MONITOR

INTERPRET

POINTER

GPIO REG

POH

MICROPROCESSOR I/F

AMCC

The S1201 is a highly-integrated VLSI device that provides

full-duplex mapping of PPP/LAPS encapsulated packets or

ATM cells into STS-12c/AU-4-4c or STS-3c/AU-4 payloads.

The S1201 supports full-duplex processing of SONET/SDH

data streams with full section, line, and path overhead pro-

cessing. The device supports framing pattern, scram-

bling/descrambling, alarm signal insertion/detection, and bit

interleaved parity (B1/B2/B3) processing. Serial interfaces for

SONET/SDH TOH overhead bytes are also provided.

The S1201 provides a line-side interface that can operate at

622.08 Mb/s (8-bit bus at 77.76 MHz) or 155.52 Mb/s (8-bit

bus at 19.44 MHz). For ATM applications, a UTOPIA Level 2

system interface, operating at either 25 or 50 MHz is pro-

vided. For Packet-over-SONET applications, a POS-PHY

Level 2 compatible interface is provided.

The S1201 is standards compliant with Bellcore GR-253, ITU

G.707, ANSI T1.105 -1995, IETF RFCs 1619/1661/1662/

2615 (PPP) and ITU-T COM 7-224-E/D307 (LAPS recom-

mendation) protocols.

ATM support includes insertion and extraction of ATM cells

into and out of the SONET/SDH SPE, scrambling/descram-

bling, header error control (HEC) detection and correction,

idle cell generation and filtering, and generation of perfor-

mance monitoring counts for TX, RX, ERR, dropped and idle

cells.

HDLC support includes framing, transparency processing,

optional 16/32 FCS processing, and self synchronous scram-

bling/descrambling (X

flow-thru mode where the system data is passed directly to or

from the SPE.

DE-SCRAMBLE

RX ATM/HDLC

(PPP/LAPS)

General Description

SCRAMBLE

CNTRS

JTAG PORT

Product Brief Revision 3.4 - February 2002

RX ATM/HDLC

CELL/PKT

(PPP/LAPS)

TX ATM/HDLC

(PPP/LAPS)

FIFO

PROC

FIFO

PROC

+1). It also supports a direct

Part Number - S1201QFI22

Production Information - The information contained in this

document is about a product in its fully tested and character-

ized phase. All features described herein are supported. Con-

tact AMCC for updates to this document and the latest product

status.

PRODUCT BRIEF

Datasheet Revision 3.1

TX_SYS_DAT[15:0]

TX_ADR[4:0]

TX_PRTY

TX_SOC(P)

TX_CLAV(PTPA)

TX_STPA

TX_ERR

TX_EOP

TX_MOD

TX_CLK

TX_ENB

RX_PRTY

RX_ENB

RX_MOD

RX_EOP

RX_ERR

RX_SYS_DAT[15:0]

RX_ADR[4:0]

RX_CLK

RX_SOC(P)

RX_CLAV(PRPA)

RX_RVAL

Related parts for S1201QFI

S1201QFI Summary of contents

Page 1

... SCRAMBLE GENERATE POH TOH MONITOR DE-SCRAMBLE MONITOR RX ATM/HDLC (PPP/LAPS) POINTER CNTRS INTERPRET TOH EXTRACT JTAG PORT GPIO REG AMCC Part Number - S1201QFI22 Datasheet Revision 3.1 PRODUCT BRIEF 43 +1). It also supports a direct TX_ERR TX_EOP TX_MOD TX_SYS_DAT[15:0] TX TX_ADR[4:0] CELL/PKT FIFO TX_CLK TX_PRTY TX ATM/HDLC ...

Page 2

S1201 STS-12c/STS-3c POS/ATM SONET Mapper Overview and Applications SONET Processing The S1201 performs standard STS-3c/STM-1 or STS-12c/(STM-4/AU-4-4c) processing for both the transmit and receive directions. ATM cells or PPP/LAPS packets are mapped into the SONET/SDH SPE/VC, the POH, TOH/SOH are ...

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