DSP56301PW80B1 Freescale Semiconductor, DSP56301PW80B1 Datasheet - Page 119

• Manufacturer Part Number: DSP56301PW80B1
• Manufacturer: Freescale Semiconductor

Specifications of DSP56301PW80B1

• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 80MHz
• Mips: 80
• Device Input Clock Speed: 80MHz
• Ram Size: 24KB
• Program Memory Size: Not RequiredKB
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: TQFP
• Lead Free Status / Rohs Status: Not Compliant

Freescale Semiconductor
M_DSR3 EQU $FFFFE3; DMA3 Source Address Register
M_DDR3 EQU $FFFFE2; DMA3 Destination Address Register
M_DCO3 EQU $FFFFE1; DMA3 Counter
M_DCR3 EQU $FFFFE0; DMA3 Control Register
;
M_DSR4 EQU $FFFFDF; DMA4 Source Address Register
M_DDR4 EQU $FFFFDE; DMA4 Destination Address Register
M_DCO4 EQU $FFFFDD; DMA4 Counter
M_DCR4 EQU $FFFFDC; DMA4 Control Register
;
M_DSR5 EQU $FFFFDB; DMA5 Source Address Register
M_DDR5 EQU $FFFFDA; DMA5 Destination Address Register
M_DCO5 EQU $FFFFD9; DMA5 Counter
M_DCR5 EQU $FFFFD8; DMA5 Control Register
;
M_DSS EQU $3
M_DSS0 EQU 0
M_DSS1 EQU 1
M_DDS EQU $C
M_DDS0 EQU 2
M_DDS1 EQU 3
M_DAM EQU $3F0 ; DMA Address Mode Mask (DAM5-DAM0)
M_DAM0 EQU 4
M_DAM1 EQU 5
M_DAM2 EQU 6
M_DAM3 EQU 7
M_DAM4 EQU 8
M_DAM5 EQU 9
M_D3D EQU 10
M_DRS EQU $F800; DMA Request Source Mask (DRS0-DRS4)
M_DCON EQU 16 ; DMA Continuous Mode
M_DPR EQU $60000; DMA Channel Priority
M_DPR0 EQU 17 ; DMA Channel Priority Level (low)
M_DPR1 EQU 18 ; DMA Channel Priority Level (high)
M_DTM EQU $380000; DMA Transfer Mode Mask (DTM2-DTM0)
M_DTM0 EQU 19 ; DMA Transfer Mode 0
M_DTM1 EQU 20 ; DMA Transfer Mode 1
M_DTM2 EQU 21 ; DMA Transfer Mode 2
M_DIE EQU 22
M_DE EQU 23
;
M_DTD EQU $3F ; Channel Transfer Done Status MASK (DTD0-DTD5)
M_DTD0 EQU 0
M_DTD1 EQU 1
M_DTD2 EQU 2
M_DTD3 EQU 3
M_DTD4 EQU 4
M_DTD5 EQU 5
M_DACT EQU 8
M_DCH EQU $E00 ; DMA Active Channel Mask (DCH0-DCH2)
M_DCH0 EQU 9
DMA Control Register
Register Addresses Of DMA4
Register Addresses Of DMA5
DMA Status Register
; DMA Source Space Mask (DSS0-Dss1)
; DMA Source Memory space 0
; DMA Source Memory space 1
; DMA Destination Space Mask (DDS-DDS1)
; DMA Destination Memory Space 0
; DMA Destination Memory Space 1
; DMA Address Mode 0
; DMA Address Mode 1
; DMA Address Mode 2
; DMA Address Mode 3
; DMA Address Mode 4
; DMA Address Mode 5
; DMA Three Dimensional Mode
; DMA Interrupt Enable bit
; DMA Channel Enable bit
; DMA Active State
; DMA Active Channel 0
; DMA Channel Transfer Done Status 0
; DMA Channel Transfer Done Status 1
; DMA Channel Transfer Done Status 2
; DMA Channel Transfer Done Status 3
; DMA Channel Transfer Done Status 4
; DMA Channel Transfer Done Status 5
DSP56301 Technical Data, Rev. 10
A-13