W255H Cypress Semiconductor Corp, W255H Datasheet

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W255H

Manufacturer Part Number
W255H
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of W255H

Lead Free Status / Rohs Status
Not Compliant

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Cypress Semiconductor Corporation
Document #: 38-07255 Rev. *C
Features
• One input to 24-output buffer/driver
• Supports up to 4 DDR DIMMs or 3 SDRAM DIMMS
• One additional output for feedback
• SMBus interface for individual output control
• Low skew outputs (< 100 ps)
• Supports 266-, 333-, and 400-MHz DDR SDRAM
• Dedicated pin for power management support
• Space-saving 48-pin SSOP package
R_DWN#
Block Diagram
SCLOCK
SEL_DDR
BUF_IN
SDATA
Power Down Control
Decoding
SMBus
3901 North First Street
200-MHz 24-Output Buffer for 4 DDR
DDR9T
DDR9C
DDR10T
DDR10C
DDR11T
DDR11C
FBOUT
DDR0T_SDRAM10
DDR0C_SDRAM11
DDR1T_SDRAM0
DDR1C_SDRAM1
DDR2T_SDRAM2
DDR2C_SDRAM3
DDR3T_SDRAM4
DDR3C_SDRAM5
DDR4T_SDRAM6
DDR4C_SDRAM7
DDR5T_SDRAM8
DDR5C_SDRAM9
DDR6T
DDR6C
DDR7T
DDR7C
DDR8T
DDR8C
Functional Description
The W255 is a 3.3V/2.5V buffer designed to distribute
high-speed clocks in PC applications. The part has 24 outputs.
Designers can configure these outputs to support four unbuf-
fered DDR DIMMS or to support three unbuffered standard
SDRAM DIMMs and two DDR DIMMS. The W255 can be used
in conjunction with the W250 or similar clock synthesizer for
the VIA Pro 266 chipset.
The W255 also includes an SMBus interface which can enable
or disable each output clock. On power-up, all output clocks
are enabled (internal pull up).
Note:
1.
DDR0C_SDRAM11
DDR0T_SDRAM10
San Jose
DDR1C_SDRAM1
DDR2C_SDRAM3
DDR3C_SDRAM5
DDR4C_SDRAM7
DDR5C_SDRAM9
DRR1T_SDRAM0
DDR2T_SDRAM2
DDR3T_SDRAM4
DDR4T_SDRAM6
DDR5T_SDRAM8
Internal 100K pull-up resistors present on inputs marked
with *. Design should not rely solely on internal pull-up resistor
to set I/O pins HIGH.
VDD3.3_2.5
VDD3.3_2.5
VDD3.3_2.5
VDD3.3_2.5
VDD3.3_2.5
or 3 SDRAM DIMMS
BUF_IN
FBOUT
SDATA
GND
GND
GND
GND
Pin Configuration
CA 95134
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Top View
Revised December 14, 2002
SSOP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDD2.5
GND
DDR7T
DDR7C
DDR6T
DDR6C
GND
SCLK
SEL_DDR*
VDD2.5
GND
DDR11T
DDR11C
DDR10T
DDR10C
VDD2.5
GND
DDR9T
DDR9C
VDD2.5
PWR_DWN#*
GND
DDR8T
DDR8C
408-943-2600
W255

Related parts for W255H

W255H Summary of contents

Page 1

... SMBus Decoding SCLOCK Power Down Control R_DWN# SEL_DDR Cypress Semiconductor Corporation Document #: 38-07255 Rev. *C 200-MHz 24-Output Buffer for 4 DDR Functional Description The W255 is a 3.3V/2.5V buffer designed to distribute high-speed clocks in PC applications. The part has 24 outputs. Designers can configure these outputs to support four unbuf- fered DDR DIMMS or to support three unbuffered standard SDRAM DIMMs and two DDR DIMMS ...

Page 2

Pin Summary Pin Name Pins SEL_DDR 48 SCLK 25 SDATA 24 BUF_IN 13 FBOUT 1 PWR_DWN# 36 DDR[6:11]T 28, 30, 34, 39, 43, 45 DDR[6:11]C 27, 29, 33, 38, 42, 44 DDR[0:5]T_SDRAM 4, 6, 10, 15, 19, 21 [10,0,2,4,6,8] DDR[0:5]C_SDRAM ...

Page 3

Serial Configuration Map • The serial bits will be read by the clock driver in the following order: Byte 0 - Bits Byte 1 - Bits ...

Page 4

Maximum Ratings Supply Voltage to Ground Potential ..................–0.5 to +7.0V DC Input Voltage (except BUF_IN) ............ –0. [2] Operating Conditions Parameter VDD3.3 Supply Voltage VDD2.5 Supply Voltage T Operating Temperature (Ambient Temperature Output Capacitance OUT C ...

Page 5

Switching Characteristics (continued) Parameter Name t DDR Falling Edge Rate 4d t Output to Output Skew for DDR 5 t Output to Output Skew for 6 [3] SDRAM t SDRAM Buffer LH Prop. Delay 7 t SDRAM Buffer HL Prop. ...

Page 6

... Figure 1 shows the differential clock directly terminated by a 120 resistor Device Out Under Test Out Figure 1. Differential Signal Using Direct Termination Resistor Ordering Information Ordering Code W255H W255HT Document #: 38-07255 Rev 60W ) 60W Package Type 48-pin SSOP 48-pin SSOP–Tape and Reel Option W255 VTR R ...

Page 7

Layout Example for DDR 2.5V Only Dale ILB1206 - 300 (300 @ 100 MHz) or TDK ACB 2012L-120 Ceramic Caps C3 = 10– VIA to GND plane layer Note: Each ...

Page 8

Layout Example SDRAM (Mixed Voltage Dale ILB1206 - 300 (300 @ 100 MHz) or TDK ACB 2012L-120 Ceramic Caps C1 and C3 = 10– VIA to GND plane layer Note: Each ...

Page 9

... Document #: 38-07255 Rev. *C © Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user ...

Page 10

Document Title: W255 200MHz 24 Output Buffer for 4 DDR or 3 SDRAM DIMMs Document Number: 38-07255 Issue REV. ECN NO. Date ** 110520 12/04/01 *A 112154 03/01/02 *B 114554 05/07/02 *C 122857 12/14/02 Document #: 38-07255 Rev. *C Orig. ...

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